公开(公告)号：US09886416B2

公开(公告)日：2018-02-06

申请号：US14733827

申请日：2015-06-08

Applicant: Intel Corporation

Inventor： Mohammad A. Abdallah

IPC: G06F15/00 ,  G06F15/80 ,  G06F7/533 ,  G06F9/30 ,  G06F9/38 ,  G06F7/483 ,  G06F7/53 ,  G06F7/544

CPC classification number: G06F15/8007 ,  G06F7/483 ,  G06F7/5318 ,  G06F7/5338 ,  G06F7/5443 ,  G06F9/3001 ,  G06F9/30109 ,  G06F9/3012 ,  G06F9/30123 ,  G06F9/30141 ,  G06F9/3016 ,  G06F9/30181 ,  G06F9/30189 ,  G06F9/3824 ,  G06F9/3828 ,  G06F9/3838 ,  G06F9/3851 ,  G06F9/3853 ,  G06F9/3867 ,  G06F9/3885 ,  G06F9/3887 ,  G06F9/3889 ,  G06F9/3891 ,  G06F15/80

Abstract: A matrix of execution blocks form a set of rows and columns. The rows support parallel execution of instructions and the columns support execution of dependent instructions. The matrix of execution blocks process a single block of instructions specifying parallel and dependent instructions.