公开(公告)号：US20190042391A1

公开(公告)日：2019-02-07

申请号：US15856427

申请日：2017-12-28

Applicant: INTEL CORPORATION

Inventor： Sankaran Menon ,  Krishna Kumar Ganesan ,  Rolf Kuehnis ,  Eija Maarit Hillevi Manninen

IPC: G06F11/36 ,  G06F11/34 ,  G06F11/30

CPC classification number: G06F11/364 ,  G06F11/302 ,  G06F11/3428 ,  G06F11/3452 ,  G06F11/3466 ,  G06F11/3636 ,  G06F2201/865

Abstract: Techniques and apparatus for error and performance analysis of a computing device are described. In one embodiment, for example, an apparatus may include at least one memory and logic coupled to the at least one memory, wherein the logic is further to access at least one trace associated with at least one trace source, access timing information associated with the at least one trace, generate a plurality of waypoints for at least one trace, each of the plurality of waypoints comprising a step of at least one trace and a time stamp, and generate at least one performance benchmark log for the at least one trace, the at least one benchmark log comprising a plurality of benchmark waypoints corresponding to the plurality of waypoints.

公开(公告)号：US09753836B2

公开(公告)日：2017-09-05

申请号：US14484427

申请日：2014-09-12

Applicant: Intel Corporation

Inventor： Sankaran Menon ,  Babu Trp ,  Rolf Kuehnis

IPC: G06F11/00 ,  G06F11/36

CPC classification number: G06F11/3648

Abstract: In an embodiment, a debug architecture for a processor/System on Chip (SoC) etc., includes a central debug unit to receive one or more functional debug signals, the central debug unit further configured to receive debug information from at least one firmware source, at least one software source, and at least one hardware source, and to output compressed debug information; a system trace module to receive the compressed debug information and to time stamp the compressed debug information; a parallel trace interface to receive the time stamped compressed debug information and to parallelize the time stamped compressed debug information; and an output unit to output the parallelized time stamped compressed debug information on one of a plurality of output paths. Other embodiments are described and claimed.

公开(公告)号：US20170003346A1

公开(公告)日：2017-01-05

申请号：US14979243

申请日：2015-12-22

Applicant: Intel Corporation

Inventor： Rolf Kuehnis ,  Robert A. Dunstan

IPC: G01R31/317 ,  G01R31/3177

CPC classification number: G01R31/043 ,  G06F9/4411 ,  G06F13/40 ,  G06F13/4068

Abstract: Techniques described herein include a method, system, and apparatus for detecting an orientation configuration. For example, an apparatus having an all-in-one port may include a first configuration pin and a second configuration pin. The apparatus may also include logic configured to enter into an accessory mode based on a presence of a first signal on the first configuration pin and a second signal on the second configuration pin. The logic may be further configured to provide an orientation indication by altering the first signal on the first configuration pin.

Abstract translation: 本文描述的技术包括用于检测取向配置的方法，系统和装置。 例如，具有一体式端口的设备可以包括第一配置引脚和第二配置引脚。 该装置还可以包括被配置为基于第一配置引脚上的第一信号的存在和第二配置引脚上的第二信号进入附件模式的逻辑。 逻辑可以进一步被配置为通过改变第一配置引脚上的第一信号来提供定向指示。