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21.发明授权Enhanced verification by closely coupling a structural satisfiability solver and rewriting algorithms 失效通过紧密耦合结构可满足性求解器和重写算法来增强验证公开(公告)号：US08015528B2
公开(公告)日：2011-09-06
申请号：US12332191
申请日：2008-12-10
IPC分类号： G06F17/50
CPC分类号： A61F13/472 , A61F13/202 , A61F13/2051 , A61F13/206 , A61F13/2065 , A61F13/2068 , G06F8/72
摘要： A method, system and computer program product are disclosed. The method includes initializing a first variable to limit a rewrite time for rewrite operations with respect to an initial design by a rewriting module, a second variable to limit a time for satisfiability solver operations with respect to said initial design by a satisfiability solver module and a third variable to limit a maximum number of rewrite iterations with respect to said initial design. A timer is called to track said rewrite time and a local logic rewriting operation is run on said initial design with said rewrite module. In response to determining that all of all targets for said initial design netlist are not solved, whether a rewrite time is expired is determined. In response to determining that said rewrite time is not expired, AND refactoring is run. In response to determining that said rewrite time is not expired, XOR refactoring is run.
摘要翻译： 公开了一种方法，系统和计算机程序产品。 该方法包括：初始化第一变量以限制由重写模块相对于初始设计的重写操作的重写时间;第二变量，用于通过可满足性求解器模块限制相对于所述初始设计的可满足性求解器操作的时间;以及 第三变量以限制相对于所述初始设计的最大重写迭代次数。 调用定时器以跟踪所述重写时间，并且利用所述重写模块在所述初始设计上运行本地逻辑重写操作。 响应于确定所有初始设计网表的所有目标未被解决，确定重写时间是否到期。 响应于确定所述重写时间未过期，并且运行重构。 响应于确定所述重写时间未过期，运行XOR重构。
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公开(公告)号：US07882473B2
公开(公告)日：2011-02-01
申请号：US11945465
申请日：2007-11-27
CPC分类号： G06F17/504
摘要： Mechanisms for performing sequential equivalence checking for asynchronous verification are provided. A first model of the integrated circuit design is provided that has additional logic in it to reflect the possible variance in behavior of the asynchronous crossings. A second model of the integrated circuit design is provided that does not have this asynchronous behavior logic but instead correlates to the simplest synchronous model that is usually used for non-asynchronous functional verification tasks. Sequential equivalence checking is performed to verify that the two models are input/output equivalent. In order to address non-uniform arrival times of bus strands, logic is provided for identifying bus strands that have transitioning bits, determining a representative delay for these strands, comparing the representative delays for all of the bus strands to determine the maximum delay for the entire bus, and applying this maximum delay to one of the models.
摘要翻译： 提供了用于执行异步验证的顺序等同性检查的机制。 提供了集成电路设计的第一个模型，其具有额外的逻辑，以反映异步交叉的行为的可能方差。 提供了集成电路设计的第二个模型，其不具有该异步行为逻辑，而是与通常用于非异步功能验证任务的最简单的同步模型相关联。 执行顺序等价检查以验证两个模型是输入/输出等效的。 为了解决总线链路的不均匀到达时间，提供了用于识别具有转换位的总线串的逻辑，确定这些线的代表性延迟，比较所有总线线的代表性延迟，以确定 整个总线，并将这个最大延迟应用于其中一个模型。
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23.发明授权Method for heuristic preservation of critical inputs during sequential reparameterization 有权在连续重新参数化过程中启发式保存关键输入的方法公开(公告)号：US07882470B2
公开(公告)日：2011-02-01
申请号：US12047189
申请日：2008-06-09
申请人： Jason R. Baumgartner , Geert Janssen , Hari Mony , Viresh Paruthi
发明人： Jason R. Baumgartner , Geert Janssen , Hari Mony , Viresh Paruthi
CPC分类号： G06F17/5045
摘要： A method, system, and computer program product for preserving critical inputs. According to an embodiments of the present invention, an initial design including one or more primary inputs which cannot be eliminated, one or more primary inputs which can be eliminated, one or more targets, and one or more state elements are received. A cut of said initial design including one or more cut gates is identified, and a relation of one or more values producible to said one or more cut gates in terms of said one or more primary inputs which cannot be eliminated, said one or more primary inputs which can be eliminated and said one or more state elements is computed. Said relation is synthesized to form a gate set, and an abstracted design is formed from said gate set. Verification is performed on said abstracted design to generate verification results.
摘要翻译： 一种用于保存关键输入的方法，系统和计算机程序产品。 根据本发明的实施例，接收包括不能被消除的一个或多个主要输入，可以被消除的一个或多个主要输入，一个或多个目标以及一个或多个状态元素的初始设计。 识别包括一个或多个切割门的所述初始设计的切割，以及根据所述一个或多个主要输入而不能被消除的一个或多个可生产到所述一个或多个切割门的值的关系，所述一个或多个主要 可以消除的输入和所述一个或多个状态元素被计算。 所述关系被合成以形成栅极集合，并且从所述栅极集合形成抽象设计。 对所述抽象设计进行验证以产生验证结果。
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24.发明申请Method and System for Automated Use of Uninterpreted Functions in Sequential Equivalence Checking 有权在顺序等价检查中自动使用未解释函数的方法和系统公开(公告)号：US20100199241A1
公开(公告)日：2010-08-05
申请号：US12362513
申请日：2009-01-30
IPC分类号： G06F17/50
CPC分类号： G06F17/504
摘要： A method, system and computer program product for automated use of uninterpreted functions in sequential equivalence checking. A first netlist and a second netlist may be received and be included in an original model, and from the original model, logic to be abstracted may be determined. A condition for functional consistency may be determined, and an abstract model may be created by replacing the logic with abstracted logic using one or more uninterpreted functions. One or more functions may be performed on the abstract model. For example, the one or more functions may include one or more of a bounded model checking (BMC) algorithm, an interpolation algorithm, a Boolean satisfiability-based analysis algorithm, and a binary decision diagram (BDD) based reachability analysis algorithm, among others.
摘要翻译： 一种在顺序等效性检查中自动使用未解释函数的方法，系统和计算机程序产品。 可以接收第一网表和第二网表并将其包括在原始模型中，并且可以从原始模型中确定要抽象的逻辑。 可以确定功能一致性的条件，并且可以通过使用一个或多个未解释函数替换具有抽象逻辑的逻辑来创建抽象模型。 抽象模型可以执行一个或多个功能。 例如，一个或多个功能可以包括有界模型检查（BMC）算法，插值算法，基于布尔可满足性的分析算法和基于二进制决策图（BDD）的可达性分析算法等中的一个或多个 。
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25.发明授权Enhanced verification by closely coupling a structural overapproximation algorithm and a structural satisfiability solver 失效通过紧密耦合结构过近似算法和结构可满足性求解器来增强验证公开(公告)号：US07743353B2
公开(公告)日：2010-06-22
申请号：US12013163
申请日：2008-01-11
IPC分类号： G06F17/50
CPC分类号： G06F17/504
摘要： A method, system and computer program product for performing verification are disclosed. A first abstraction of an initial design netlist containing a first target is created and designated as a current abstraction, and the current abstraction is unfolded by a selectable depth. A composite target is verified using a satisfiability solver, and in response to determining that the verifying step has hit the composite target, a counterexample to is examined to identify one or more reasons for the first target to be asserted. One or more refinement pairs are built by examining the counterexample, and a second abstraction is built by composing the refinement pairs. One or more learned clauses and one or more invariants to the second abstraction and the second abstraction is chosen as the current abstraction. The current abstraction is verified with the satisfiability solver.
摘要翻译： 公开了一种用于执行验证的方法，系统和计算机程序产品。 创建包含第一个目标的初始设计网表的第一个抽象，并将其指定为当前抽象，并且当前抽象由可选深度展开。 使用可满足性求解器验证复合目标，并且响应于确定验证步骤已经击中复合目标，检查反例以识别要被断言的第一目标的一个或多个原因。 通过检查反例来构建一个或多个细化对，并通过组合细化对构建第二个抽象。 选择一个或多个学习子句和一个或多个第二抽象和第二抽象的不变量作为当前抽象。 目前的抽象是用可满足性求解器来验证的。
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26.发明授权Generating constraint preserving testcases in the presence of dead-end constraints 有权在存在死区约束的情况下生成约束保留测试用例公开(公告)号：US07600209B2
公开(公告)日：2009-10-06
申请号：US11673298
申请日：2007-02-09
IPC分类号： G06F17/50
CPC分类号： G06F17/5022
摘要： Mechanisms for generating constraint preserving testcases in the presence of dead-end constraints are provided. A balance between precision and computational expense in generating the testcases is achieved by establishing a sliding window of constraint solving for a selected number of K time-steps in the future from a current time-step. The testcases solve for the constraints for the next K time-steps at every state of a netlist instead of just trying to solve the constraint for the present time-step. K is determined by determining, for each input, either a minimum length path depth or maximum length depth path from the input to the constraint. The largest depth value for the inputs to the netlist is then utilized as the depth for the netlist. This depth then is used to define the width of the sliding window of constraint solving.
摘要翻译： 提供了在存在死区约束的情况下生成约束保留测试用例的机制。 在生成测试用例时，精度和计算费用之间的平衡是通过从当前时间步骤中为将来选定数量的K个时间步骤建立一个约束求解滑动窗口来实现的。 测试用例解决了网表的每个状态下的下一个K时间步长的约束，而不是仅仅尝试解决当前时间步长的约束。 通过为每个输入确定从输入到约束的最小长度路径深度或最大长度深度路径来确定K。 网表的输入的最大深度值随后被用作网表的深度。 此深度用于定义约束求解的滑动窗口的宽度。
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27.发明申请公开(公告)号：US20080270086A1
公开(公告)日：2008-10-30
申请号：US12168469
申请日：2008-07-07
IPC分类号： G06F17/50
CPC分类号： G06F17/504
摘要： A system for performing verification includes a means for: importing a design netlist containing component(s), computing output function(s) for the component(s), generating output equivalent state set(s) from the output function(s), identifying next-state function(s) for the component(s), means for producing image equivalent state set(s) for the next-state function(s), means for classifying output-and-image equivalent state set(s) for the image equivalent state set(s) and the output equivalent state set(s), getting a preimage from the next-state function(s) and the output-and-image equivalent state(s) to generate a preimage of the output-and-image equivalent state(s), partitioning over original state(s) of the component(s), and equivalent class input set(s) of the component(s). Moreover, the system includes a means for: selecting input representative(s) of the equivalent input set(s), forming an input map from the input representative(s), synthesizing the input map, and injecting the input map back into the netlist to generate a modified netlist.
摘要翻译： 用于执行验证的系统包括用于：导入包含组件的设计网表，计算组件的计算输出功能，从输出功能生成输出等效状态集合的装置，识别 用于组件的下一状态功能，用于产生用于下一状态功能的图像等价状态集合的装置，用于对用于下一状态功能的输出和图像等效状态集合进行分类的装置 图像等效状态集合和输出等效状态集合，从下一状态函数获得预图像和输出和图像等效状态以生成输出的前图像，以及 图像等效状态，对组件的原始状态进行分区，以及组件的等效类输入集合。 此外，该系统包括一种装置，用于：选择等效输入组的输入代表，从输入代表形成输入图，合成输入图，并将输入图反映回网表中 以生成修改的网表。
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28.发明授权Method for predicate-based compositional minimization in a verification environment 失效在验证环境中基于谓词的组合最小化方法公开(公告)号：US07437690B2
公开(公告)日：2008-10-14
申请号：US11249937
申请日：2005-10-13
IPC分类号： G06F17/50
CPC分类号： G06F17/504
摘要： A method for performing verification includes importing a design netlist containing one or more components and computing one or more output functions for the one or more components. One or more output equivalent state sets are generated from the one or more output functions and one or more next-state functions for the one or more components are identified. One or more image equivalent state sets for the one or more next-state functions are produced and one or more output-and-image equivalent state sets are classified for the one or more image equivalent state sets and the one or more output equivalent state sets. One or more input representatives of the one or more equivalent input sets are selected and an input map is formed from the one or more input representatives. The input map is synthesized and injected back into the netlist to generate a modified netlist.
摘要翻译： 执行验证的方法包括导入包含一个或多个组件的设计网表，并计算一个或多个组件的一个或多个输出功能。 从一个或多个输出功能产生一个或多个输出等效状态集合，并且识别一个或多个组件的一个或多个下一个状态功能。 产生用于一个或多个下一状态函数的一个或多个图像等效状态集合，并且对于一个或多个图像等效状态集合和一个或多个输出等效状态集合分类一个或多个输出和图像等效状态集合 。 选择一个或多个等效输入集合的一个或多个输入代表，并且从一个或多个输入代表形成输入映射。 输入图合成并注入网表以生成修改的网表。
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29.发明申请METHOD AND SYSTEM FOR PERFORMING TARGET ENLARGEMENT IN THE PRESENCE OF CONSTRAINTS 失效在限制条件下执行目标放大的方法和系统公开(公告)号：US20080216029A1
公开(公告)日：2008-09-04
申请号：US12036093
申请日：2008-02-22
IPC分类号： G06F17/50
CPC分类号： G06F17/504
摘要： A method for performing verification is disclosed. The method includes receiving a design, including one or one or more targets, one or more constraints, one or more registers and one or more inputs. A first function of one of the one or more targets over the one or more registers and the one or more inputs is computed. A second function of one or more of the one or more constraints over the one or more registers and the one or more inputs is computed. The inputs of the first function and the second function are existentially quantified. A bounded analysis is performed to determine if the one of the one or more targets may be hit while adhering to the constraints. A preimage of the inputs of the first function and a preimage of the inputs of the second function is existentially quantified to create a synthesizable preimage. The synthesizable preimage is simplified and synthesized to create an enlarged target. Verification of the enlarged target is performed.
摘要翻译： 公开了一种用于执行验证的方法。 该方法包括接收包括一个或多个目标，一个或多个约束，一个或多个寄存器和一个或多个输入的设计。 计算一个或多个寄存器中的一个或多个目标之一和一个或多个输入的第一函数。 计算一个或多个寄存器和一个或多个输入中的一个或多个约束中的一个或多个的第二函数。 第一功能和第二功能的输入被存在量化。 执行有界分析以确定一个或多个目标中的一个是否可以在遵守约束的情况下被击中。 存在量化第一函数的输入和第二函数的输入的前像的前像，以创建可合成的前像。 可合成的前像被简化和合成，以创建一个扩大的目标。 执行放大目标的验证。
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公开(公告)号：US07360181B2
公开(公告)日：2008-04-15
申请号：US11382533
申请日：2006-05-10
IPC分类号： G06F17/50
CPC分类号： G06F17/504
摘要： A method for identifying isomorphic cones with sub-linear resources by exploiting reflexivities, the method comprising: identifying a gate g1 and a gate g2 in a netlist; mapping source gates of g1 with any permutation of source gates of g2 by using calls to an isomorphism detection algorithm; determining whether a permutation exists of pairings between the gates sourcing g1 and g2; resetting pairing of gates if the permutation exists; and eliminating pairwise-identical source gates of g1 and g2.
摘要翻译： 一种用于通过利用反射性识别具有子线性资源的同构锥体的方法，所述方法包括：在网表中识别门g 1和门g 2; 通过使用对同构检测算法的调用，将g 1的源栅格映射到g 2的源极的任何排列; 确定在源出g 1和g 2之间的配对是否存在置换; 如果置换存在，重置门的配对; 并且消除了g 1和g 2的成对相同的源极。
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