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1.发明授权公开(公告)号：US08086429B2
公开(公告)日：2011-12-27
申请号：US12168469
申请日：2008-07-07
CPC分类号： G06F17/504
摘要： A system for performing verification includes a means for: importing a design netlist containing component(s), computing output function(s) for the component(s), generating output equivalent state set(s) from the output function(s), identifying next-state function(s) for the component(s), means for producing image equivalent state set(s) for the next-state function(s), means for classifying output-and-image equivalent state set(s) for the image equivalent state set(s) and the output equivalent state set(s), getting a preimage from the next-state function(s) and the output-and-image equivalent state(s) to generate a preimage of the output-and-image equivalent state(s), partitioning over original state(s) of the component(s), and equivalent class input set(s) of the component(s). Moreover, the system includes a means for: selecting input representative(s) of the equivalent input set(s), forming an input map from the input representative(s), synthesizing the input map, and injecting the input map back into the netlist to generate a modified netlist.
摘要翻译： 用于执行验证的系统包括用于：导入包含组件的设计网表，计算组件的计算输出功能，从输出功能生成输出等效状态集合的装置，识别 用于组件的下一状态功能，用于产生用于下一状态功能的图像等价状态集合的装置，用于对用于下一状态功能的输出和图像等效状态集合进行分类的装置 图像等效状态集合和输出等效状态集合，从下一状态函数获得预图像和输出和图像等效状态以生成输出的前图像，以及 图像等效状态，对组件的原始状态进行分区，以及组件的等效类输入集合。 此外，该系统包括一种装置，用于：选择等效输入组的输入代表，从输入代表形成输入图，合成输入图，并将输入图反映回网表中 以生成修改的网表。
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公开(公告)号：US20080270086A1
公开(公告)日：2008-10-30
申请号：US12168469
申请日：2008-07-07
IPC分类号： G06F17/50
CPC分类号： G06F17/504
摘要： A system for performing verification includes a means for: importing a design netlist containing component(s), computing output function(s) for the component(s), generating output equivalent state set(s) from the output function(s), identifying next-state function(s) for the component(s), means for producing image equivalent state set(s) for the next-state function(s), means for classifying output-and-image equivalent state set(s) for the image equivalent state set(s) and the output equivalent state set(s), getting a preimage from the next-state function(s) and the output-and-image equivalent state(s) to generate a preimage of the output-and-image equivalent state(s), partitioning over original state(s) of the component(s), and equivalent class input set(s) of the component(s). Moreover, the system includes a means for: selecting input representative(s) of the equivalent input set(s), forming an input map from the input representative(s), synthesizing the input map, and injecting the input map back into the netlist to generate a modified netlist.
摘要翻译： 用于执行验证的系统包括用于：导入包含组件的设计网表，计算组件的计算输出功能，从输出功能生成输出等效状态集合的装置，识别 用于组件的下一状态功能，用于产生用于下一状态功能的图像等价状态集合的装置，用于对用于下一状态功能的输出和图像等效状态集合进行分类的装置 图像等效状态集合和输出等效状态集合，从下一状态函数获得预图像和输出和图像等效状态以生成输出的前图像，以及 图像等效状态，对组件的原始状态进行分区，以及组件的等效类输入集合。 此外，该系统包括一种装置，用于：选择等效输入组的输入代表，从输入代表形成输入图，合成输入图，并将输入图反映回网表中 以生成修改的网表。
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3.发明授权Method for predicate-based compositional minimization in a verification environment 失效在验证环境中基于谓词的组合最小化方法公开(公告)号：US07437690B2
公开(公告)日：2008-10-14
申请号：US11249937
申请日：2005-10-13
IPC分类号： G06F17/50
CPC分类号： G06F17/504
摘要： A method for performing verification includes importing a design netlist containing one or more components and computing one or more output functions for the one or more components. One or more output equivalent state sets are generated from the one or more output functions and one or more next-state functions for the one or more components are identified. One or more image equivalent state sets for the one or more next-state functions are produced and one or more output-and-image equivalent state sets are classified for the one or more image equivalent state sets and the one or more output equivalent state sets. One or more input representatives of the one or more equivalent input sets are selected and an input map is formed from the one or more input representatives. The input map is synthesized and injected back into the netlist to generate a modified netlist.
摘要翻译： 执行验证的方法包括导入包含一个或多个组件的设计网表，并计算一个或多个组件的一个或多个输出功能。 从一个或多个输出功能产生一个或多个输出等效状态集合，并且识别一个或多个组件的一个或多个下一个状态功能。 产生用于一个或多个下一状态函数的一个或多个图像等效状态集合，并且对于一个或多个图像等效状态集合和一个或多个输出等效状态集合分类一个或多个输出和图像等效状态集合 。 选择一个或多个等效输入集合的一个或多个输入代表，并且从一个或多个输入代表形成输入映射。 输入图合成并注入网表以生成修改的网表。
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4.发明授权公开(公告)号：US08141048B2
公开(公告)日：2012-03-20
申请号：US11677652
申请日：2007-02-22
CPC分类号： G06F8/43
摘要： A method of verifying a software system includes receiving a description of a software system described utilizing a high-level modeling language, and responsive thereto, parsing the description and constructing an abstract syntax graph. The abstract syntax graph is transformed into a sequential logic representation of the software system. The sequential logic representation is formed by reference to a Hardware Description Language (HDL) library. Then, the sequential logic representation is transformed into a gate-level sequential logic representation. Following the transforming, the software system is verified based upon the gate-level sequential logic representation. Following verification, results of verification of the software system are output.
摘要翻译： 验证软件系统的方法包括接收使用高级建模语言描述的软件系统的描述，并且响应于此，解析描述并构造抽象语法图。 抽象语法图被转换成软件系统的顺序逻辑表示。 通过参考硬件描述语言（HDL）库形成顺序逻辑表示。 然后，顺序逻辑表示被转换成门级顺序逻辑表示。 在变换之后，基于门级顺序逻辑表示验证软件系统。 验证后，输出软件系统的验证结果。
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5.发明申请Method, System and Program Product Supporting Sequential Encoding for Relational Analysis (SERA) of a Software Model 有权方法，系统和程序产品支持软件模型的关系分析（SERA）的顺序编码公开(公告)号：US20080209389A1
公开(公告)日：2008-08-28
申请号：US11677652
申请日：2007-02-22
IPC分类号： G06F9/44
CPC分类号： G06F8/43
摘要： A method of verifying a software system includes receiving a description of a software system described utilizing a high-level modeling language, and responsive thereto, parsing the description and constructing an abstract syntax graph. The abstract syntax graph is transformed into a sequential logic representation of the software system, and following the transforming, the software system is verified based upon the sequential logic representation. Following verification, results of verification of the software system are output.
摘要翻译： 验证软件系统的方法包括接收使用高级建模语言描述的软件系统的描述，并且响应于此，解析描述并构造抽象语法图。 抽象语法图被转换为软件系统的顺序逻辑表示，并且在变换之后，基于顺序逻辑表示验证软件系统。 验证后，输出软件系统的验证结果。
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公开(公告)号：US20100058256A1
公开(公告)日：2010-03-04
申请号：US12202500
申请日：2008-09-02
申请人： ALI S. EL-ZEIN , Fadi A. Zaraket
发明人： ALI S. EL-ZEIN , Fadi A. Zaraket
IPC分类号： G06F17/50
CPC分类号： G06F17/505 , G06F2217/86 , Y02T10/82
摘要： Co-Optimization utilizing Symbolic Execution (COSE) works across components of an embedded design to optimize structures therein. COSE utilizes symbolic execution (SE) to analyze software components and defines a limited set of values that software feeds hardware as constraints. SE explores substantially all possible paths of execution of the code specifying a component. It accomplishes this by accumulating path conditions (PCs) and annotating them to the corresponding segments of the component. A PC is associated with a branch of code and consists of the conjunction of conditions over input and state variables necessary and sufficient for the branch to execute. These PCs define constraints that limit the set of values that software feeds hardware. These constraints are then propagated across the networks of the design and employ static analysis techniques such as constant propagation, redundancy removal, and don't care optimizations to reduce the hardware components.
摘要翻译： 利用符号执行（COSE）的协同优化在嵌入式设计的组件中工作，以优化其中的结构。 COSE利用符号执行（SE）来分析软件组件，并定义一组有限的值，软件将硬件提供给约束。 SE基本上探索了指定组件的代码的所有可能的执行路径。 它通过累积路径条件（PC）并将其注释到组件的相应段来实现。 PC与代码分支相关联，并且由对分支执行所必需的足够的输入和状态变量的条件的结合组成。 这些PC定义了限制软件提供硬件的值集合的约束。 然后，这些约束在设计网络中传播，并采用静态分析技术，例如恒定传播，冗余删除，并且不关心优化以减少硬件组件。
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7.发明申请TECHNIQUES FOR MODELING VARIABLES IN SUBPROGRAMS OF HARDWARE DESCRIPTION LANGUAGE PROGRAMS 有权用于在硬件描述语言程序的子规范中建立变量的技术公开(公告)号：US20090193390A1
公开(公告)日：2009-07-30
申请号：US12022309
申请日：2008-01-30
IPC分类号： G06F9/44
CPC分类号： G06F17/5045 , G06F9/4484
摘要： A method, system and computer program product for modeling variables in subprograms of a HDL program. A subprogram is provided with an initial value of a variable of an element being modeled and the subprogram is stored in memory of a data processing system. In response to a subprogram call, a copy of the stored subprogram is provided to the requesting HDL program. During execution, the initial value of the variable in the provided copy of the subprogram may be modified by the HDL program, but the value retains unchanged in the stored subprogram.
摘要翻译： 一种用于对HDL程序子程序中的变量进行建模的方法，系统和计算机程序产品。 子程序被提供有被建模的元件的变量的初始值，并且子程序被存储在数据处理系统的存储器中。 响应于子程序调用，将所存储的子程序的副本提供给请求的HDL程序。 在执行期间，子程序提供的副本中的变量的初始值可以由HDL程序修改，但是该值在存储的子程序中保持不变。
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8.发明授权公开(公告)号：US08140313B2
公开(公告)日：2012-03-20
申请号：US12022309
申请日：2008-01-30
IPC分类号： G06F17/50
CPC分类号： G06F17/5045 , G06F9/4484
摘要： A method, system and computer program product for modeling variables in subprograms of a HDL program. A subprogram is provided with an initial value of a variable of an element being modeled and the subprogram is stored in memory of a data processing system. In response to a subprogram call, a copy of the stored subprogram is provided to the requesting HDL program. During execution, the initial value of the variable in the provided copy of the subprogram may be modified by the HDL program, but the value retains unchanged in the stored subprogram.
摘要翻译： 一种用于对HDL程序子程序中的变量进行建模的方法，系统和计算机程序产品。 子程序被提供有被建模的元件的变量的初始值，并且子程序被存储在数据处理系统的存储器中。 响应于子程序调用，将所存储的子程序的副本提供给请求的HDL程序。 在执行期间，子程序提供的副本中的变量的初始值可以由HDL程序修改，但是该值在存储的子程序中保持不变。
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