公开(公告)号：US08589327B2

公开(公告)日：2013-11-19

申请号：US13092262

申请日：2011-04-22

Applicant: Jason R. Baumgartner ,  Michael L. Case ,  Robert L. Kanzelman ,  Hari Mony

Inventor： Jason R. Baumgartner ,  Michael L. Case ,  Robert L. Kanzelman ,  Hari Mony

IPC: G06F17/00 ,  G06N5/02

CPC classification number: G06F17/504 ,  G06F17/11 ,  G06F2217/06

Abstract: A mechanism is provided for efficiently determining Boolean satisfiability (SAT) using lazy constraints. A determination is made as to whether a SAT problem is satisfied without constraints in a list of constraints. Responsive to the SAT problem being satisfied without constraints, a set of variable assignments that are determined in satisfying the SAT problem without constraints are fixed. For each constraint in the list of constraints, a determination is made as to whether the SAT problem with the constraint results in the set of variable assignments remaining constant. Responsive to the SAT problem with the constraint resulting in the set of variable assignments remaining constant, the constraint is added to a list of non-affecting constraints and a satisfied result is returned.

Abstract translation: 提供了一种使用延迟约束有效地确定布尔可满足性（SAT）的机制。 确定SAT问题是否满足约束列表中的约束。 响应于没有约束的满足SAT问题的SAT问题，在不受约束的情况下满足SAT问题确定的一组可变分配是固定的。 对于约束列表中的每个约束，确定具有约束的SAT问题是否导致可变分配集合保持不变。 响应于导致变量赋值集合保持不变的约束的SAT问题，约束被添加到不受影响的约束的列表，并且返回满意的结果。

公开(公告)号：US08418106B2

公开(公告)日：2013-04-09

申请号：US12872490

申请日：2010-08-31

Applicant: Jason R. Baumgartner ,  Michael L. Case ,  Robert L. Kanzelman ,  Hari Mony

Inventor： Jason R. Baumgartner ,  Michael L. Case ,  Robert L. Kanzelman ,  Hari Mony

IPC: G06F17/50

CPC classification number: G06F17/504

Abstract: A technique for performing an analysis of a logic design (that includes a native memory array embodied in a netlist) includes detecting an initial transient behavior in the logic design as embodied in the netlist. The technique also includes determining a duration of the initial transient behavior and gathering reduction information on the logic design based on the initial transient behavior. The netlist is then modified based on the reduction information.

Abstract translation: 用于执行对逻辑设计（包括在网表中包含的本地存储器阵列）的分析的技术包括检测在网表中体现的逻辑设计中的初始瞬态行为。 该技术还包括基于初始瞬态行为来确定初始瞬态行为的持续时间并收集关于逻辑设计的减少信息。 然后基于减少信息来修改网表。

公开(公告)号：US20120290992A1

公开(公告)日：2012-11-15

申请号：US13104573

申请日：2011-05-10

Applicant: Michael L. Case ,  Jason R. Baumgartner ,  Robert L. Kanzelman ,  Hari Mony

Inventor： Michael L. Case ,  Jason R. Baumgartner ,  Robert L. Kanzelman ,  Hari Mony

IPC: G06F17/50

CPC classification number: G06F17/505

Abstract: A logic synthesis program, method and system for simplifying and/or reducing a logic design receives output from a logic simulator that uses symbolic values for stimulus and contains symbolic values in the logic simulator output. Relationships between the nodes dependent on symbolic values can be used to merge nodes or otherwise simplify the logic design. Behaviors such as oscillators, transient values, identical signals, dependent logical states and chicken-switch determined states that depend on the symbolic values can be detected in the simulation results and the netlist simplified using the results of the detection. The netlist can be simplified by inserting registers to represent nodes that assume a symbolic value or combination based on symbolic values either statically or after an initial transient. Oscillating nodes can be replaced with equivalent oscillator circuits, and nodes having values dependent on chicken-switch operation can be detected and replaced with registers initialized from the chicken-switch input states.

Abstract translation: 用于简化和/或减少逻辑设计的逻辑综合程序，方法和系统从逻辑模拟器接收输出，该逻辑模拟器使用符号值作为刺激，并在逻辑模拟器输出中包含符号值。 依赖于符号值的节点之间的关系可用于合并节点或简化逻辑设计。 可以在仿真结果和使用检测结果简化的网表中检测到依赖于符号值的振荡器，瞬态值，相同信号，依赖逻辑状态和鸡开关确定状态等行为。 可以通过插入寄存器来简化网表，以代表以静态方式或初始瞬态之后基于符号值假设符号值或组合的节点。 振荡节点可以用等效的振荡器电路代替，并且可以检测具有取决于鸡开关操作的值的节点，并用从鸡开关输入状态初始化的寄存器替换振荡节点。

公开(公告)号：US08146034B2

公开(公告)日：2012-03-27

申请号：US12771677

申请日：2010-04-30

Applicant: Jason R. Baumgartner ,  Michael L. Case ,  Robert L. Kanzelman ,  Hari Mony

Inventor： Jason R. Baumgartner ,  Michael L. Case ,  Robert L. Kanzelman ,  Hari Mony

IPC: G06F17/50

CPC classification number: G06F17/5022 ,  G06F17/504

Abstract: A mechanism is provided for efficient redundancy identification, redundancy removal, and sequential equivalence checking with designs including memory arrays. The mechanism includes an array merging component to optimally merge an array output such that if the address is out-of-bounds or the port is not asserted, the array output is converted to a random output. The mechanism also includes a component for determining the equivalence of enabled array outputs rather than the array outputs directly and creating an enabled array output. The mechanism also includes a component that precludes potentially-redundant array cells from participating in the sequential redundancy removal determination. This component first checks for compatibility of the corresponding arrays, then the corresponding read port enables and addresses, then the corresponding initial values, and finally checking that writes to the corresponding columns yield a compatible set of values.

Abstract translation: 提供了一种机制，用于有效的冗余识别，冗余删除和与包括存储器阵列的设计的顺序等同性检查。 该机制包括阵列合并组件，以最佳地合并阵列输出，以便如果地址超出边界或端口未被断言，阵列输出将转换为随机输出。 该机制还包括用于确定启用的阵列输出的等效性的组件，而不是直接对阵列输出进行创建并创建启用的阵列输出。 该机制还包括排除潜在冗余阵列单元参与顺序冗余移除确定的组件。 该组件首先检查相应阵列的兼容性，然后对应的读端口启用和地址，然后对应的初始值，最后检查对相应列的写入是否产生兼容的值集合。

公开(公告)号：US08122403B2

公开(公告)日：2012-02-21

申请号：US12425095

申请日：2009-04-16

Applicant: Jason R. Baumgartner ,  Robert L. Kanzelman ,  Hari Mony ,  Viresh Paruthi

Inventor： Jason R. Baumgartner ,  Robert L. Kanzelman ,  Hari Mony ,  Viresh Paruthi

IPC: G06F9/455 ,  G06F17/50

CPC classification number: G06F17/504

Abstract: Methods and systems are provided for producing more efficient digital circuitry designs by identifying trace-containment for a sequential circuitry design netlist through the use of constraint-based uncorrelated equivalence checking. A set of candidate input netlist sets n1 and n2 is first uncorrelated and then submitted for equivalence checking. Mismatches discovered during the equivalence checking are avoided by imposing constraint to the input set until discovering an equivalency relationship between the input sets n1 and n2.

Abstract translation: 提供了方法和系统，用于通过使用基于约束的不相关等价检查来识别顺序电路设计网表的跟踪容纳来产生更有效的数字电路设计。 一组候选输入网表集n1和n2首先不相关，然后提交用于等价检查。 在等效检查期间发现的不匹配通过对输入集施加约束来避免，直到发现输入集n1和n2之间的等价关系。

公开(公告)号：US07373624B2

公开(公告)日：2008-05-13

申请号：US11225672

申请日：2005-09-13

Applicant: Jason R. Baumgartner ,  Robert L. Kanzelman ,  Hari Mony ,  Viresh Paruthi

Inventor： Jason R. Baumgartner ,  Robert L. Kanzelman ,  Hari Mony ,  Viresh Paruthi

IPC: G06F17/50 ,  G06F9/45 ,  G06F7/60

CPC classification number: G06F17/504

Abstract: A method for performing verification is disclosed. The method includes receiving a design, including one or one or more targets, one or more constraints, one or more registers and one or more inputs. A first function of one of the one or more targets over the one or more registers and the one or more inputs is computed. A second function of one or more of the one or more constraints over the one or more registers and the one or more inputs is computed. The inputs of the first function and the second function are existentially quantified. A bounded analysis is performed to determine if the one of the one or more targets may be hit while adhering to the constraints. A preimage of the inputs of the first function and a preimage of the inputs of the second function is existentially quantified to create a synthesizable preimage. The synthesizable preimage is simplified and synthesized to create an enlarged target. Verification of the enlarged target is performed.

Abstract translation: 公开了一种用于执行验证的方法。 该方法包括接收包括一个或多个目标，一个或多个约束，一个或多个寄存器和一个或多个输入的设计。 计算一个或多个寄存器中的一个或多个目标之一和一个或多个输入的第一函数。 计算一个或多个寄存器和一个或多个输入中的一个或多个约束中的一个或多个的第二函数。 第一功能和第二功能的输入被存在量化。 执行有界分析以确定一个或多个目标中的一个是否可以在遵守约束的情况下被击中。 存在量化第一函数的输入和第二函数的输入的前像的前像，以创建可合成的前像。 可合成的前像被简化和合成，以创建一个扩大的目标。 执行放大目标的验证。

公开(公告)号：US07315996B2

公开(公告)日：2008-01-01

申请号：US11232764

申请日：2005-09-22

Applicant: Jason R. Baumgartner ,  Robert L. Kanzelman ,  Hari Mony ,  Viresh Paruthi

Inventor： Jason R. Baumgartner ,  Robert L. Kanzelman ,  Hari Mony ,  Viresh Paruthi

IPC: G06F17/50

CPC classification number: G06F17/504

Abstract: A method for performing verification is disclosed. The method includes selecting a first computer-design constraint for simplification and applying structural reparameterization to simplify the first computer-design constraint. In response to determining that the first computer-design constraint is not eliminated, the first computer-design constraint is set equal to a dead-end state of the constraint. A structural preimage of the first computer-design constraint is created, in response to determining that a combination of a target and the dead-end state of the first computer-design constraint is equal to a combination of the target and the structural preimage of the first computer-design constraint, the first computer-design constraint is set equal to the structural preimage.

Abstract translation: 公开了一种用于执行验证的方法。 该方法包括选择第一计算机设计约束以简化并应用结构重新参数化以简化第一计算机设计约束。 响应于确定第一计算机设计约束不被消除，第一计算机设计约束被设置为等于约束的死端状态。 响应于确定第一计算机设计约束的目标和死端状态的组合等于目标和第一计算机设计约束的结构前图像的组合，创建第一计算机设计约束的结构预图像 第一个计算机设计约束，第一个计算机设计约束被设置为等于结构前像。

公开(公告)号：US5537330A

公开(公告)日：1996-07-16

申请号：US258314

申请日：1994-06-10

Applicant: Robert F. Damiano ,  Anthony D. Drumm ,  Michael K. Edwards ,  Robert L. Kanzelman ,  Kathy M. McCarthy

Inventor： Robert F. Damiano ,  Anthony D. Drumm ,  Michael K. Edwards ,  Robert L. Kanzelman ,  Kathy M. McCarthy

IPC: G06F17/50

CPC classification number: G06F17/505

Abstract: A method within a logic synthesis system provides for using tags attached to the nodes in a parse string generated from an abstract description of a logic design to classify portions of a heterogeneous design as open control, structure dominant, or direct map. The classification is then used to govern the amount of optimization allowed during logic synthesis. The classification is further used to seed or bypass the covering algorithms to produce the technology implementation desired by the designer. Structure dominance is a technique for "seeding" patterns by a designer which best fit the structure to the technology, which implies that the structural representation of the design as entered by the designer dominates the patterns located by the covering algorithm. However, other pattern matching functions are allowed to find better matches, if they exist, and the covering algorithm is allowed the final choice. Direct map processing bypasses optimization and covering altogether to implement the structural representation exactly as written, if possible, using the available elements in the target technology library. In the event that direct map is not possible, the node is processed as structure dominant.

Abstract translation: 逻辑综合系统中的方法提供使用从逻辑设计的抽象描述生成的解析字符串中的节点附加标签，以将异构设计的部分分类为开放控制，结构主导或直接映射。 然后，分类用于管理在逻辑合成期间允许的优化量。 分类进一步用于种子或绕过覆盖算法以产生设计者期望的技术实现。 结构优势是一种设计人员将“结构化”模式最适合于技术结构的技术，这意味着由设计者输入的设计结构表示主导了覆盖算法所定位的模式。 然而，其他模式匹配函数可以找到更好的匹配，如果它们存在，并且允许覆盖算法是最终选择。 如果可能，使用目标技术库中的可用元素，直接映射处理将绕过优化和覆盖，以完全实现结构化表示。 在直接映射不可能的情况下，节点被处理为结构主导。

公开(公告)号：US08589837B1

公开(公告)日：2013-11-19

申请号：US13455839

申请日：2012-04-25

Applicant: Jason R. Baumgartner ,  Michael L. Case ,  Robert L. Kanzelman ,  Hari Mony

Inventor： Jason R. Baumgartner ,  Michael L. Case ,  Robert L. Kanzelman ,  Hari Mony

IPC: G06F17/50

CPC classification number: G06F17/505 ,  G06F17/504

Abstract: A computer-implemented method simplifies a netlist, verifies the simplified netlist using induction, and remaps resulting inductive counterexamples via inductive trace lifting within a multi-algorithm verification framework. The method includes: a processor deriving a first unreachable state information that can be utilized to simplify the netlist; performing a simplification of the netlist utilizing the first unreachable state information; determining whether the first unreachable state information can be inductively proved on an original version of the netlist; and in response to the first unreachable state information not being inductively provable on the original netlist: projecting the first unreachable state information to a minimal subset; and adding the projected unreachable state information as an invariant to further constrain a child induction process. Adding the projected state information as an invariant ensures that any resulting induction counterexamples can be mapped to valid induction counterexamples on the original netlist before undergoing the simplification.

Abstract translation: 计算机实现的方法简化网表，使用归纳验证简化的网表，并通过多算法验证框架内的归纳跟踪提升重新生成归纳反例。 该方法包括：处理器导出可用于简化网表的第一不可达状态信息; 利用第一不可达状态信息来执行网表的简化; 确定在网表的原始版本上是否可以感应地证明第一不可达状态信息; 并且响应于在原始网表上不被感应地证明的第一不可达状态信息：将第一不可达状态信息投射到最小子集; 并且将预测的不可达状态信息添加为不变量以进一步约束儿童归纳过程。 将投影状态信息添加为不变量确保在进行简化之前，任何导致的归因反例可以映射到原始网表上的有效归纳反例。

公开(公告)号：US08307313B2

公开(公告)日：2012-11-06

申请号：US12775607

申请日：2010-05-07

Applicant: Jason R. Baumgartner ,  Michael L. Case ,  Robert L. Kanzelman ,  Hari Mony

Inventor： Jason R. Baumgartner ,  Michael L. Case ,  Robert L. Kanzelman ,  Hari Mony

IPC: G06F17/50 ,  G06F9/455 ,  G06F15/16

CPC classification number: G06F17/505

Abstract: Mechanisms are provided in a design environment for minimizing memory array representations for enhanced synthesis and verification. The design environment comprises one mechanism to compress the width of arrays using disconnected pin information. The design environment comprises another mechanism to simplify the enable conditions of array ports using “don't care” computations. The design environment comprises yet another mechanism to reduce address pins from an array through analysis of limitations of readable addresses.

Abstract translation: 在用于最小化存储器阵列表示以用于增强的合成和验证的设计环境中提供机制。 设计环境包括使用断开的引脚信息压缩阵列宽度的一种机制。 设计环境包括使用无关心计算简化阵列端口使能条件的另一种机制。 设计环境包括通过分析可读地址的限制来减少地址引脚从阵列的另一机制。