Method and system for building binary decision diagrams efficiently in a structural network representation of a digital circuit
    21.
    发明授权
    Method and system for building binary decision diagrams efficiently in a structural network representation of a digital circuit 有权
    在数字电路的结构网络表示中有效构建二进制决策图的方法和系统

    公开(公告)号:US07340473B2

    公开(公告)日:2008-03-04

    申请号:US10926587

    申请日:2004-08-26

    IPC分类号: G06F17/50

    摘要: A method, system and computer program product for building decision diagrams efficiently in a structural network representation of a digital circuit using a dynamic resource constrained and interleaved depth-first-search and modified breadth-first-search schedule is disclosed. The method includes setting a first size limit for a first set of one or more m-ary decision representations describing a logic function and setting a second size limit for a second set of one or more m-ary decision representations describing a logic function. The first set of m-ary decision representations of the logic function is then built with one of the set of a depth-first technique or a breadth-first technique until the first size limit is reached, and a second set of m-ary decision representations of the logic function is built with the other technique until the second size limit is reached. In response to determining that a union of first set and the second set of m-ary decision representations do not describe the logic function, the first and second size limits are increased, and the steps of building the first and second set are repeated. In response to determining that the union of the first set of m-ary decision representations and the second set of m-ary decision representations describe the logic function, the union is reported.

    摘要翻译: 公开了一种用于在使用动态资源约束和交织的深度优先搜索和修改的宽度优先搜索时间表的数字电路的结构网络表示中有效地构建决策图的方法,系统和计算机程序产品。 该方法包括:对描述逻辑功能的一个或多个多元决策表示的第一集合设置第一大小限制,并为描述逻辑功能的一个或多个虚拟决策表示的第二组设置第二大小限制。 然后,利用深度优先技术或宽度优先技术的集合之一构建逻辑功能的第一组m元决定表示,直到达到第一大小限制,并且第二组m元决定 使用其他技术构建逻辑功能的表示,直到达到第二个大小限制。 响应于确定第一集合和第二组m元决定表示的并集不描述逻辑函数,增加第一和第二大小限制,并且重复构建第一集合和第二集合的步骤。 响应于确定第一组m元决策表示和第二组m元决策表示的并集描述逻辑函数,报告联合。

    Method For Verification Using Reachability Overapproximation
    22.
    发明申请
    Method For Verification Using Reachability Overapproximation 失效
    使用可达性过近似的验证方法

    公开(公告)号:US20080066031A1

    公开(公告)日:2008-03-13

    申请号:US11938656

    申请日:2007-11-12

    IPC分类号: G06F17/50

    CPC分类号: G06F17/504

    摘要: A method, system and computer program product for verifying that a design conforms to a desired property is disclosed. The method comprises receiving a design, a first initial state of the design, and a property for verification with respect to the design. The first initial state of the design is expanded to create a superset of the first initial state containing one or more states reachable from the first initial state of the design. A superset is synthesized to define a second initial state of the design. Application of the superset to the design is overapproximated through cutpoint insertion into the superset to obtain a modified superset, and the property is verified with reference to the modified superset.

    摘要翻译: 公开了一种用于验证设计符合期望属性的方法,系统和计算机程序产品。 该方法包括接收设计,设计的第一初始状态和关于设计的验证的属性。 设计的第一初始状态被扩展以创建包含从设计的第一初始状态可访问的一个或多个状态的第一初始状态的超集。 合成超集以定义设计的第二初始状态。 超设计对设计的应用通过将切入点插入到超集中来获得修改后的超集,并且参考修改后的超集来验证该属性。

    Method for Verification Using Reachability Overapproximation
    23.
    发明申请
    Method for Verification Using Reachability Overapproximation 失效
    使用可达性过近似验证的方法

    公开(公告)号:US20080052650A1

    公开(公告)日:2008-02-28

    申请号:US11938612

    申请日:2007-11-12

    IPC分类号: G06F17/50

    CPC分类号: G06F17/504

    摘要: A method, system and computer program product for verifying that a design conforms to a desired property is disclosed. The method comprises receiving a design, a first initial state of the design, and a property for verification with respect to the design. The first initial state of the design is expanded to create a superset of the first initial state containing one or more states reachable from the first initial state of the design. A superset is synthesized to define a second initial state of the design. Application of the superset to the design is overapproximated through cutpoint insertion into the superset to obtain a modified superset, and the property is verified with reference to the modified superset.

    摘要翻译: 公开了一种用于验证设计符合期望属性的方法,系统和计算机程序产品。 该方法包括接收设计,设计的第一初始状态和关于设计的验证的属性。 设计的第一初始状态被扩展以创建包含从设计的第一初始状态可访问的一个或多个状态的第一初始状态的超集。 合成超集以定义设计的第二初始状态。 超设计对设计的应用通过将切入点插入到超集中来获得修改后的超集,并且参考修改后的超集来验证该属性。

    Method for retiming in the presence of verification constraints
    24.
    发明授权
    Method for retiming in the presence of verification constraints 失效
    在存在验证约束的情况下重新定时的方法

    公开(公告)号:US07203915B2

    公开(公告)日:2007-04-10

    申请号:US11077331

    申请日:2005-03-10

    IPC分类号: G06F17/50

    CPC分类号: G06F17/504

    摘要: A method, system and computer program product for performing retiming in the presence of constraints are disclosed. The method comprises receiving an initial design containing one or more targets and one or more constraints and enumerating the one or more constraints and the one or more targets into a retiming gate set. A retiming graph is constructed from the initial design, and a retiming solution is obtained on the retiming graph. The retiming solution is normalized. One or more retiming lags from the retiming graph are propagated to the initial design, and the initial design is verified by using a constraint-satisfying analysis to determine whether the one or more targets may be hit while the one or more constraints are satisfied.

    摘要翻译: 公开了一种用于在存在约束的情况下执行重新定时的方法,系统和计算机程序产品。 该方法包括接收包含一个或多个目标和一个或多个约束的初始设计,并将一个或多个约束和一个或多个目标列举到重定时门组中。 从初始设计构建重新定时图,并在重新定时图上获得重新定时解决方案。 重新定时解决方案被归一化。 来自重新定时图的一个或多个重新定时延迟被传播到初始设计,并且通过使用约束满足分析来确认初始设计,以确定在满足一个或多个约束的情况下是否可以命中一个或多个目标。

    Using constraints in design verification
    25.
    发明申请
    Using constraints in design verification 有权
    在设计验证中使用约束

    公开(公告)号:US20070074136A1

    公开(公告)日:2007-03-29

    申请号:US11236451

    申请日:2005-09-27

    IPC分类号: G06F17/50

    CPC分类号: G06F17/504

    摘要: A method for generating a constraint for use in the verification of an integrated circuit design includes identifying a target in a netlist (N) of the design and creating an overapproximate abstraction (N′) of the netlist. A space state (S′) is created by enumerating the states of N′ from which the identified target may be asserted. A constraint space C′ is then derived from the state space S′, where C′ is the logical complement of S′. The process is repeated for multiple selected targets and the constraint spaces from each iteration are logically ANDed. Creating an overapproximate abstraction may include replacing a sequential gate with a random gate. Identifying a sequential gate may include selecting a target in the netlist, performing underapproximate verification of the target, and, if a spurious failure occurs, selecting a gate further down the fanin chain of the currently selected gate.

    摘要翻译: 一种用于生成用于验证集成电路设计的约束的方法包括识别设计的网表(N)中的目标并创建网表的过近似抽象(N')。 通过枚举从其识别出的目标可以被断言的N'的状态来创建空间状​​态(S')。 然后从状态空间S'导出约束空间C',其中C'是S'的逻辑补码。 对于多个选定的目标重复该过程,并且来自每个迭代的约束空间被逻辑地进行AND。 创建过近似抽象可能包括用随机门替换顺序门。 识别顺序门可以包括选择网表中的目标,执行目标的近似不正确的验证,并且如果发生虚假故障,则选择进一步向下沿当前选择的门的扇形链的门。

    Method for verification using reachability overapproximation
    26.
    发明申请
    Method for verification using reachability overapproximation 有权
    使用可达性过近似验证的方法

    公开(公告)号:US20060129958A1

    公开(公告)日:2006-06-15

    申请号:US11011245

    申请日:2004-12-14

    IPC分类号: G06F17/50 G06F9/45

    CPC分类号: G06F17/504

    摘要: A method, system and computer program product for verifying that a design conforms to a desired property is disclosed. The method comprises receiving a design, a first initial state of the design, and a property for verification with respect to the design. The first initial state of the design is expanded to create a superset of the first initial state containing one or more states reachable from the first initial state of the design. A superset is synthesized to define a second initial state of the design. Application of the superset to the design is overapproximated through cutpoint insertion into the superset to obtain a modified superset, and the property is verified with reference to the modified superset.

    摘要翻译: 公开了一种用于验证设计符合期望属性的方法,系统和计算机程序产品。 该方法包括接收设计,设计的第一初始状态和关于设计的验证的属性。 设计的第一初始状态被扩展以创建包含从设计的第一初始状态可访问的一个或多个状态的第一初始状态的超集。 合成超集以定义设计的第二初始状态。 超设计对设计的应用通过将切入点插入到超集中来获得修改后的超集,并且参考修改后的超集来验证该属性。