Event counter
    21.
    发明授权
    Event counter 有权
    事件柜台

    公开(公告)号:US08122079B2

    公开(公告)日:2012-02-21

    申请号:US12089056

    申请日:2006-10-04

    CPC classification number: G07C3/04 G11C16/349

    Abstract: A counting method and a counter using an integrated circuit memory area, including at least one step of storage of partial values in several words of identical memory sizes, the result of the counting being obtained by arithmetically adding the values contained in the different words.

    Abstract translation: 一种使用集成电路存储区域的计数方法和计数器,包括至少一个存储相同存储器大小的几个字的部分值的步骤,通过算术地添加包含在不同字中的值来获得计数的结果。

    Event Counter
    22.
    发明申请
    Event Counter 有权
    事件柜台

    公开(公告)号:US20080219400A1

    公开(公告)日:2008-09-11

    申请号:US12089056

    申请日:2006-10-04

    CPC classification number: G07C3/04 G11C16/349

    Abstract: A counting method and a counter using an integrated circuit memory area, including at least one step of storage of partial values in several words of identical memory sizes, the result of the counting being obtained by arithmetically adding the values contained in the different words.

    Abstract translation: 一种使用集成电路存储区域的计数方法和计数器,包括至少一个存储相同存储器大小的几个字的部分值的步骤,通过算术地添加包含在不同字中的值来获得计数的结果。

    Detection of a sequencing error in the execution of a program
    23.
    发明申请
    Detection of a sequencing error in the execution of a program 审中-公开
    检测程序执行中的排序错误

    公开(公告)号:US20060265578A1

    公开(公告)日:2006-11-23

    申请号:US11437416

    申请日:2006-05-19

    CPC classification number: G06F11/28

    Abstract: The automatic control of the execution of a program by a microprocessor, including storing an initial state of a counter before execution of at least one instruction comprising the execution a given number of times of at least one same operation; on each execution of the operation, incrementing or decrementing the counter by a weight assigned to the operation; and at the end of the instruction, comparing the final state of the counter with an estimated value by increasing, respectively decreasing, its initial state by a multiple of the weight assigned to the operation corresponding to the normal number of executions of this operation in the instruction.

    Abstract translation: 微处理器对程序执行的自动控制,包括在执行包括执行至少一个相同操作的给定次数的至少一个指令之前存储计数器的初始状态; 在每次执行操作时,通过分配给操作的权重递增或递减计数器; 并且在指令结束时,将计数器的最终状态与估计值进行比较,通过将其初始状态分别递减与分配给与该操作的正常执行次数相对应的操作的权重的倍数 指令。

    Method of key derivation in an integrated circuit
    24.
    发明授权
    Method of key derivation in an integrated circuit 有权
    集成电路中的关键推导方法

    公开(公告)号:US08964975B2

    公开(公告)日:2015-02-24

    申请号:US13615251

    申请日:2012-09-13

    CPC classification number: H04L9/003 H04L9/0861 H04L9/0891 H04L2209/12

    Abstract: A method of derivation, by an electronic circuit, of a first key from a second key, wherein: at least one third key is derived from the second key and is used to derive the first key; and a value of a counter, representative of the number of first keys, conditions the derivation of a new value of the third key.

    Abstract translation: 一种通过电子电路从第二密钥推导第一密钥的方法,其中:从所述第二密钥导出至少一个第三密钥,并用于导出所述第一密钥; 代表第一密钥数量的计数器的值,条件是导出第三密钥的新值。

    Control of the execution of a program
    25.
    发明申请
    Control of the execution of a program 有权
    控制程序的执行

    公开(公告)号:US20050289270A1

    公开(公告)日:2005-12-29

    申请号:US11146719

    申请日:2005-06-07

    CPC classification number: G06F21/54 G06F21/552

    Abstract: A method and a circuit of automatic control of the execution of a program by a microprocessor, including: assigning a digital decrement or increment to at least one function of the program; assigning a digital increment, respectively decrement, to at least one section considered as critical as to the program execution and called by the function; setting a counter to a first value; decrementing, respectively incrementing, the counter once per function before a call to a critical section; incrementing, respectively decrementing, the counter on each correct execution of a section; and comparing the current value of the counter with a predetermined critical threshold.

    Abstract translation: 一种由微处理器自动控制程序执行的方法和电路,包括:向程序的至少一个功能分配数字递减或增量; 将数字增量分别递减至被认为对于程序执行至关重要并由功能调用的至少一个部分; 将一个计数器设置为第一个值; 在调用临界区之前,每个功能递减计数器一次; 每个正确执行部分递增递减计数器; 以及将所述计数器的当前值与预定临界阈值进行比较。

    Interface between a twin-wire bus and a single-wire bus
    26.
    发明授权
    Interface between a twin-wire bus and a single-wire bus 有权
    双线总线和单线总线之间的接口

    公开(公告)号:US08161224B2

    公开(公告)日:2012-04-17

    申请号:US12502634

    申请日:2009-07-14

    CPC classification number: G06F13/4282 G06F13/4027 G06F2213/0016

    Abstract: A method and a device for converting a first bus including at least a data wire and a clock wire into a single-wire bus, wherein a data bit of the first bus is converted on half a period of the clock signal for transmission over the second bus, a waiting pattern being placed on the second bus during the other half-period.

    Abstract translation: 一种用于将包括至少数据线和时钟线的第一总线转换成单线总线的方法和装置,其中第一总线的数据位在时钟信号的半个周期上被转换,以在第二总线上传输第二总线 公共汽车,在另一半期间,等待方式被放置在第二辆公共汽车上。

    Method of automatic control of the execution of a program by a microprocessor
    27.
    发明授权
    Method of automatic control of the execution of a program by a microprocessor 有权
    通过微处理器自动控制程序执行的方法

    公开(公告)号:US07496738B2

    公开(公告)日:2009-02-24

    申请号:US11146719

    申请日:2005-06-07

    CPC classification number: G06F21/54 G06F21/552

    Abstract: A method and a circuit of automatic control of the execution of a program by a microprocessor, including: assigning a digital decrement or increment to at least one function of the program; assigning a digital increment, respectively decrement, to at least one section considered as critical as to the program execution and called by the function; setting a counter to a first value; decrementing, respectively incrementing, the counter once per function before a call to a critical section; incrementing, respectively decrementing, the counter on each correct execution of a section; and comparing the current value of the counter with a predetermined critical threshold.

    Abstract translation: 一种由微处理器自动控制程序执行的方法和电路,包括:向程序的至少一个功能分配数字递减或增量; 将数字增量分别递减至被认为对于程序执行至关重要并由功能调用的至少一个部分; 将一个计数器设置为第一个值; 在调用临界区之前,每个功能递减计数器一次; 每个正确执行部分递增递减计数器; 以及将所述计数器的当前值与预定临界阈值进行比较。

    Protection of a microcontroller
    28.
    发明申请

    公开(公告)号:US20060112436A1

    公开(公告)日:2006-05-25

    申请号:US11283096

    申请日:2005-11-18

    CPC classification number: G06F21/52 G06F21/55 H04W12/12

    Abstract: A method for protecting at least one section of a program executed by a microcontroller, included before execution of the section, decrementing or incrementing at least one first counter and storing its state in a non-volatile memory of the microcontroller; in case of the detection of an attack attempt by the microcontroller, activating a flag in the microcontroller RAM; and at the end of the execution of the program section, checking the flag state.

    Verification of data read in memory
    29.
    发明授权
    Verification of data read in memory 有权
    在内存中读取的数据的验证

    公开(公告)号:US08775697B2

    公开(公告)日:2014-07-08

    申请号:US12743684

    申请日:2008-10-18

    CPC classification number: G06F21/606 G06F21/755

    Abstract: A method and a circuit for checking data transferred between a circuit and a processing unit, in which: the data originating from the circuit transit through a first buffer element having a size which is a multiple of the size of data to be subsequently delivered over a bus of the processing unit; an address provided by the processing unit for the circuit is temporarily stored in a second element; and the content of the first element is compared with current data originating from the circuit, at least when they correspond to an address of data already present in this first element.

    Abstract translation: 一种用于检查在电路和处理单元之间传送的数据的方法和电路,其中:从电路发出的数据通过第一缓冲元件,该第一缓冲元件的尺寸是要随后传送的数据的大小的倍数 总线处理单元; 由电路处理单元提供的地址暂时存储在第二元件中; 并且将第一元素的内容与来自电路的当前数据进行比较,至少当它们对应于已经存在于该第一元素中的数据的地址时。

    Non-volatile memory counter
    30.
    发明授权
    Non-volatile memory counter 有权
    非易失性存储器计数器

    公开(公告)号:US08660233B2

    公开(公告)日:2014-02-25

    申请号:US13560476

    申请日:2012-07-27

    CPC classification number: H03K21/00 G11C16/349 H03K21/403

    Abstract: A counter in a non-volatile memory including at least two sub-counters, each counting with a different modulo, an increment of the counter being transferred on a single one of the sub-counters and the sub-counters being incremented sequentially.

    Abstract translation: 包括至少两个子计数器的非易失性存储器中的计数器,每个副计数器以不同的模计数,在单个子计数器上传送的计数器的增量和子计数器依次递增。

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