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    Methods and apparatus to preform inter-integrated circuit address modification
    2.
    发明授权
    Methods and apparatus to preform inter-integrated circuit address modification 有权

    公开(公告)号：US12124393B2

    公开(公告)日：2024-10-22

    申请号：US17587695

    申请日：2022-01-28

    申请人： Texas Instruments Incorporated

    发明人： Deric Wayne Waters ,  Xiaoxi Bruce Zhang

    IPC分类号： G06F13/40 ,  G06F13/42

    CPC分类号： G06F13/4068 ,  G06F13/4282 ,  G06F2213/0016

    摘要： An example system includes: a device coupled to a data line, the device configured to: send a first command on the data line, the first command including a first address; after sending the first command, read a first value on the data line, the first value including data from a first target device and a second target device; responsive to reading the first value, send a second command including the first address and data representing the first value on the data line; send a third command on the data line, the third command including the first address; after sending the third command, read a second value on the data line, the second value including data from the first target device and the second target device; responsive to reading the second value, send a fourth command on the data line, the fourth command including the first address.

    Electronic devices and methods of controlling power in electronic devices
    4.
    发明授权
    Electronic devices and methods of controlling power in electronic devices 有权

    公开(公告)号：US12034373B2

    公开(公告)日：2024-07-09

    申请号：US17575249

    申请日：2022-01-13

    申请人： SAMSUNG ELECTRONICS CO., LTD.

    发明人： Sangwook Park ,  Joonseok Park ,  Jongjin Lee ,  Horang Jang

    IPC分类号： H02M3/158 ,  G06F13/42 ,  H02M3/157

    CPC分类号： H02M3/1584 ,  G06F13/4282 ,  H02M3/157 ,  G06F2213/0016 ,  G06F2213/0038

    摘要： An electronic device includes a system on chip (SoC) and a power management integrated circuit (PMIC). The SoC includes a plurality of power domains and a dynamic voltage and frequency scaling (DVFS) controller which performs DVFS on the power domains The PMIC includes direct current (DC)-DC converters and a control logic which controls the plurality of DC-DC converters, and each of the DC-DC converters provides a corresponding output voltage to a respective one of the power domains. The control logic designates a target DC-DC converter which provides a target output voltage having a target level as a global DC-DC converter and provides the target output voltage to a power domain corresponding the global DC-DC converter and to at least one first power domain consuming the target output voltage, from among the plurality of power domains, by sharing the target output voltage provided by the global DC-DC converter.

    Method of data synchronization and redundant server system
    5.
    发明授权
    Method of data synchronization and redundant server system 有权

    公开(公告)号：US12013798B2

    公开(公告)日：2024-06-18

    申请号：US18052559

    申请日：2022-11-03

    申请人： Mitac Computing Technology Corporation

    发明人： Chin-Hung Tan ,  Heng-Chia Hsu ,  Chien-Chung Wang ,  Yu-Shu Yeh ,  Chen-Yin Lin

    IPC分类号： G06F9/445 ,  G06F13/16

    CPC分类号： G06F13/1668 ,  G06F9/44505 ,  G06F2213/0016

    摘要： A method of data synchronization is to be implemented by a redundant server system including an active input/output module (IOM) and a passive IOM. The method includes: allocating a primary transfer buffer in the active IOM; allocating a secondary transfer buffer in the passive IOM; collecting pieces of secondary dedicated-sensor data, and storing the pieces of secondary dedicated-sensor data in the primary transfer buffer at once; collecting pieces of primary dedicated-sensor data; after the pieces of primary dedicated-sensor data have been collected, updating the primary state data based on the pieces of primary dedicated-sensor data thus collected and the pieces of secondary dedicated-sensor data stored in the primary transfer buffer at once, and storing the primary state data thus updated in the secondary transfer buffer; and updating the secondary state data based on the primary state data that have been updated and that are stored in the secondary transfer buffer.

    I2C bridge device
    8.
    发明授权
    I2C bridge device 有权

    公开(公告)号：US11928066B2

    公开(公告)日：2024-03-12

    申请号：US16470264

    申请日：2017-12-15

    申请人： Iristick NV

    发明人： Jasper Van Bourgognie ,  Vianney Le Clément de Saint-Marcq ,  Riemer Grootjans ,  Peter Verstraeten

    IPC分类号： G06F13/40 ,  G06F13/42 ,  H04L5/14

    CPC分类号： G06F13/4045 ,  G06F13/4031 ,  G06F13/4291 ,  H04L5/14 ,  G06F2213/0016

    摘要： The present invention relates to a bridge device operable between a master device and a slave device of a communication system, said master device and said slave device arranged for communicating with each other via a parent I2C bus and a child I2C bus and using the I2C protocol, said bridge device comprising—a parent module arranged for connecting said parent I2C bus and comprising a parent I2C transmitter/receiver device and a parent module state machine, —a child module arranged for connecting said child I2C bus and comprising a child I2C transmitter/receiver device and a child module state machine, whereby said parent module and said child module each comprise an internal bridge interface to exchange messages between said parent module and said child module, said messages being generated by said parent module state machine or said child module state machine in response to a change of state caused by an event on their respective I2C buses, whereby said parent module and said child module are each arranged for translating an I2C event to a message and for forwarding said message to the module at the other side of the bridge device via said internal bridge interfaces, said module at the other side being arranged for further transmitting said message as an I2C event towards the I2C bus at the other side of the bridge device, and whereby said parent module and said child module are further each arranged for holding the communication towards the respective I2C bus by stretching a clock line on their respective I2C bus until a message, based on an event occurring on the I2C bus at the other side of the bridge device and instructing continuation of the communication, is received via said internal bridge interfaces from the module at the other side of the bridge device.

    Clock synchronization system and operation method thereof capable of synchronizing operation time of internal circuits
    10.
    发明授权
    Clock synchronization system and operation method thereof capable of synchronizing operation time of internal circuits 有权

    公开(公告)号：US11892871B2

    公开(公告)日：2024-02-06

    申请号：US17684443

    申请日：2022-03-02

    申请人： Realtek Semiconductor Corp.

    发明人： Po-Lin Wei ,  Ching-Lung Chen

    IPC分类号： G06F1/12 ,  G06F13/42

    CPC分类号： G06F1/12 ,  G06F13/4291 ,  G06F2213/0016 ,  G06F2213/0042

    摘要： A host circuit includes a first clock generator, a first input output interface, a first communication interface, and a first processor. The first clock generator generates a first clock signal. The first processor outputs a trigger signal through the first input output interface, records a first clock count of the first clock generator at the same time, and outputs the first clock count through the first communication interface. A slave circuit includes a second clock generator, a second input output interface, a second communication interface, and a second processor. The second clock generator generates a second clock signal. When receiving the trigger signal, the second processor records a second clock count of the second clock generator, and calculates a time difference between the first clock signal and the second clock signal according to the first clock count and the second clock count.