Non-toxic stabilizer for halogenated polymer
    21.
    发明授权
    Non-toxic stabilizer for halogenated polymer 失效
    卤化聚合物的无毒稳定剂

    公开(公告)号:US4988750A

    公开(公告)日:1991-01-29

    申请号:US907127

    申请日:1986-09-11

    CPC classification number: C08K5/58

    Abstract: What are disclosed are a non-toxic stabilizer mixture for a molding compound comprising a halogenated polymer, said stabilizer mixture comprising about 40 percent by weight of a didodecyltin-bis-thioglycolic acid ester of the formula(n-C.sub.12 H.sub.25).sub.2 Sn(SCH.sub.2 COOR).sub.2and about 60 percent by weight of a dodecyltin-tristhioglycolic acid ester of the formulan-C.sub.12 H.sub.25 Sn(SCH.sub.2 COOR).sub.3wherein R is a straight-chain or branched-chain alkyl having 8 to 20 carbon atoms, a method for stabilizing a halogenated molding compound with such a stabilizer mixture, and a stabilized molding compound comprising such a stabilizer mixture.

    Abstract translation: 公开的是用于包含卤化聚合物的模塑料的无毒稳定剂混合物,所述稳定剂混合物包含约40重量%的式(n-C12H25)2Sn(SCH2COOR)2的二癸基锡 - 双 - 巯基乙酸酯 和约60重量%的式n-C12H25Sn(SCH2COOR)3的十二烷基锡 - 三硫代乙酸酯,其中R是具有8至20个碳原子的直链或支链烷基,稳定卤化模塑料的方法 使用这种稳定剂混合物,以及包含这种稳定剂混合物的稳定的模塑料。

    Micro-Electromechanical System Devices
    22.
    发明申请
    Micro-Electromechanical System Devices 失效
    微机电系统设备

    公开(公告)号:US20120061734A1

    公开(公告)日:2012-03-15

    申请号:US13300138

    申请日:2011-11-18

    CPC classification number: B81C1/00246 B81B2201/0271 B81C2203/0742

    Abstract: Micro-electromechanical system (MEMS) devices and methods of manufacture thereof are disclosed. In one embodiment, a MEMS device includes a semiconductive layer disposed over a substrate. A trench is disposed in the semiconductive layer, the trench with a first sidewall and an opposite second sidewall. A first insulating material layer is disposed over an upper portion of the first sidewall, and a conductive material disposed within the trench. An air gap is disposed between the conductive material and the semiconductive layer.

    Abstract translation: 公开了微机电系统(MEMS)装置及其制造方法。 在一个实施例中,MEMS器件包括设置在衬底上的半导体层。 沟槽设置在半导体层中,沟槽具有第一侧壁和相对的第二侧壁。 第一绝缘材料层设置在第一侧壁的上部之上,并且设置在沟槽内的导电材料。 在导电材料和半导体层之间设置气隙。

    Micro-electromechanical system devices
    23.
    发明授权
    Micro-electromechanical system devices 有权
    微机电系统设备

    公开(公告)号:US08125046B2

    公开(公告)日:2012-02-28

    申请号:US12133104

    申请日:2008-06-04

    CPC classification number: B81C1/00246 B81B2201/0271 B81C2203/0742

    Abstract: Micro-electromechanical system (MEMS) devices and methods of manufacture thereof are disclosed. In one embodiment, a MEMS device includes a semiconductive layer disposed over a substrate. A trench is disposed in the semiconductive layer, the trench with a first sidewall and an opposite second sidewall. A first insulating material layer is disposed over an upper portion of the first sidewall, and a conductive material disposed within the trench. An air gap is disposed between the conductive material and the semiconductive layer.

    Abstract translation: 公开了微机电系统(MEMS)装置及其制造方法。 在一个实施例中,MEMS器件包括设置在衬底上的半导体层。 沟槽设置在半导体层中,沟槽具有第一侧壁和相对的第二侧壁。 第一绝缘材料层设置在第一侧壁的上部之上,并且设置在沟槽内的导电材料。 在导电材料和半导体层之间设置气隙。

    Semiconductor Devices and Methods of Manufacture Thereof
    24.
    发明申请
    Semiconductor Devices and Methods of Manufacture Thereof 有权
    半导体器件及其制造方法

    公开(公告)号:US20110195565A1

    公开(公告)日:2011-08-11

    申请号:US13091612

    申请日:2011-04-21

    CPC classification number: H01L21/743

    Abstract: Semiconductor devices and methods of manufacture thereof are disclosed. In one embodiment, a semiconductor device includes a workpiece having a buried layer disposed beneath a top portion thereof. A trench is disposed in the workpiece extending at least through the buried layer. At least one sinker contact is disposed in the top portion of the workpiece. The at least one sinker contact is proximate sidewalls of at least a portion of the trench and is adjacent the buried layer. An insulating material is disposed on the sidewalls of the trench. A conductive material is disposed within the trench and is coupled to a lower portion of the workpiece.

    Abstract translation: 公开了半导体器件及其制造方法。 在一个实施例中,半导体器件包括具有设置在其顶部下方的掩埋层的工件。 沟槽设置在至少延伸穿过掩埋层的工件中。 至少一个沉降片触点设置在工件的顶部。 所述至少一个沉降片接触件邻近所述沟槽的至少一部分的侧壁并且与所述掩埋层相邻。 绝缘材料设置在沟槽的侧壁上。 导电材料设置在沟槽内并联接到工件的下部。

    WORKSPACE DIVIDING SYSTEM
    25.
    发明申请
    WORKSPACE DIVIDING SYSTEM 审中-公开
    工作空间分拣系统

    公开(公告)号:US20080148658A1

    公开(公告)日:2008-06-26

    申请号:US11854272

    申请日:2007-09-12

    CPC classification number: E04B2/7416 A47B83/001 E04B2002/7483

    Abstract: A system for dividing a workspace includes first and second vertically extending walls having a respective upper and lower edge and respective side edges. The first and second walls are arranged in parallel to partially enclose an area. A ceiling is included that extends between the first and second walls to join the upper edges of the first and second walls and at least partially cover the partially enclosed area. The resulting arch-shaped divider system may include any of a plurality of features. For example, the systems may include integrated work surfaces, informational areas, or may include viewing passages and may be arranged in a variety of configurations designed to facilitate collaborative work.

    Abstract translation: 用于分割工作空间的系统包括具有相应的上边缘和下边缘以及相应侧边缘的第一和第二垂直延伸壁。 第一和第二壁平行布置以部分地包围一个区域。 包括在第一和第二壁之间延伸以连接第一和第二壁的上边缘并且至少部分地覆盖部分封闭区域的天花板。 所得到的拱形分隔系统可以包括多个特征中的任何一个。 例如,系统可以包括集成的工作表面,信息区域,或者可以包括观看通道,并且可以以旨在促进协同工作的各种配置来布置。

    Semiconductor circuit arrangement and a method for producing same
    26.
    发明授权
    Semiconductor circuit arrangement and a method for producing same 有权
    半导体电路装置及其制造方法

    公开(公告)号:US06852585B2

    公开(公告)日:2005-02-08

    申请号:US10148379

    申请日:2000-11-30

    CPC classification number: H01L29/66484 H01L27/0629 H01L29/1079 H01L29/7831

    Abstract: A semiconductor circuit arrangement includes a circuit element embedded in a semiconductor substrate of a first conductivity type in an integrated manner and is provided with at least one gate electrode and first and second terminal electrodes. The first terminal electrode includes a well region that is embedded in the semiconductor substrate and is of a second conductivity type which is opposite the first conductivity type. A sub-well region is embedded in the well region of the first terminal electrode and is of the second conductivity type and has a higher doping than said well region. The sub-well region is embedded in the surface of the substrate and ends without reaching a well region of the gate electrode which is of the first conductivity type.

    Abstract translation: 半导体电路装置包括以一体化方式嵌入第一导电类型的半导体衬底中的电路元件,并且设置有至少一个栅极电极和第一和第二端子电极。 第一端子电极包括嵌入在半导体衬底中且与第一导电类型相反的第二导电类型的阱区。 子阱区域嵌入在第一端子电极的阱区域中并且是第二导电类型并且具有比所述阱区域更高的掺杂。 子阱区域嵌入在衬底的表面中并且结束而不到达第一导电类型的栅电极的阱区。

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