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    SEMICONDUCTOR MEMORY DEVICE WITH MEMORY CELLS OPERATED BY BOOSTED VOLTAGE
    24.
    发明申请
    SEMICONDUCTOR MEMORY DEVICE WITH MEMORY CELLS OPERATED BY BOOSTED VOLTAGE 有权
    具有由升压电压操作的存储器电池的半导体存储器件

    公开(公告)号：US20080247220A1

    公开(公告)日：2008-10-09

    申请号：US12133343

    申请日：2008-06-04

    申请人： Masanao Yamaoka ,  Kenichi Osada ,  Koichiro Ishibashi

    发明人： Masanao Yamaoka ,  Kenichi Osada ,  Koichiro Ishibashi

    IPC分类号： G11C11/00

    CPC分类号： G11C11/417 ,  G11C11/412 ,  Y10S257/903

    摘要： A memory using an SRAM memory cell intended for low-voltage operation is designed to decrease the threshold value of MOS transistors constituting the memory cell without substantial decrease in the static noise margin, which is the operational margin of the memory cell. To this end, a voltage Vdd′ higher than a power supply voltage Vdd of a power supply line for peripheral circuits is supplied from a power supply line for memory cells as a power supply voltage for memory cells. Since the conductance of driver MOS transistors is in-creased, the threshold voltage of the MOS transistors within the memory cells can be reduced without reducing the static noise margin. Further the ratio of width between the driver MOS transistor and a transfer MOS transistor can be set to 1, thereby allowing a reduction in the memory cell area.

    摘要翻译： 使用用于低电压操作的SRAM存储单元的存储器被设计为降低构成存储器单元的MOS晶体管的阈值，而不会显着降低静态噪声容限，这是存储单元的操作余量。 为此，作为存储单元的电源电压，从用于存储单元的电源线提供高于外围电路用电源线的电源电压Vdd的电压Vdd'。 由于驱动器MOS晶体管的电导被增加，所以可以在不降低静态噪声容限的情况下减小存储单元内的MOS晶体管的阈值电压。 此外，可以将驱动器MOS晶体管和转移MOS晶体管之间的宽度比设置为1，从而允许存储单元区域的减小。

    Semiconductor memory device with memory cells operated by boosted voltage
    25.
    发明授权
    Semiconductor memory device with memory cells operated by boosted voltage 有权
    具有由升压电压工作的存储单元的半导体存储器件

    公开(公告)号：US07190609B2

    公开(公告)日：2007-03-13

    申请号：US10926032

    申请日：2004-08-26

    申请人： Masanao Yamaoka ,  Kenichi Osada ,  Koichiro Ishibashi

    发明人： Masanao Yamaoka ,  Kenichi Osada ,  Koichiro Ishibashi

    IPC分类号： G11C11/00

    CPC分类号： G11C11/417 ,  G11C11/412 ,  Y10S257/903

    摘要： A memory using an SRAM memory cell intended for low-voltage operation is designed to decrease the threshold value of MOS transistors constituting the memory cell without substantial decrease in the static noise margin, which is the operational margin of the memory cell. To this end, a voltage Vdd′ higher than a power supply voltage Vdd of a power supply line for peripheral circuits is supplied from a power supply line for memory cells as a power supply voltage for memory cells. Since the conductance of driver MOS transistors is increased, the threshold voltage of the MOS transistors within the memory cells can be reduced without reducing the static noise margin. Further the ratio of width between the driver MOS transistor and a transfer MOS transistor can be set to 1, thereby allowing a reduction in the memory cell area.

    摘要翻译： 使用用于低电压操作的SRAM存储单元的存储器被设计为降低构成存储器单元的MOS晶体管的阈值，而不会显着降低静态噪声容限，这是存储单元的操作余量。 为此，作为存储单元的电源电压，从用于存储单元的电源线提供高于外围电路用电源线的电源电压Vdd的电压Vdd'。 由于驱动器MOS晶体管的电导增加，所以可以在不降低静态噪声容限的情况下减小存储单元内的MOS晶体管的阈值电压。 此外，可以将驱动器MOS晶体管和转移MOS晶体管之间的宽度比设置为1，从而允许存储单元区域的减小。

    Semiconductor memory device with memory cells operated by boosted voltage
    26.
    发明申请
    Semiconductor memory device with memory cells operated by boosted voltage 有权
    具有由升压电压工作的存储单元的半导体存储器件

    公开(公告)号：US20070133260A1

    公开(公告)日：2007-06-14

    申请号：US11657026

    申请日：2007-01-24

    申请人： Masanao Yamaoka ,  Kenichi Osada ,  Koichiro Ishibashi

    发明人： Masanao Yamaoka ,  Kenichi Osada ,  Koichiro Ishibashi

    IPC分类号： G11C11/00

    CPC分类号： G11C11/417 ,  G11C11/412 ,  Y10S257/903

    摘要： A memory using an SRAM memory cell intended for low-voltage operation is designed to decrease the threshold value of MOS transistors constituting the memory cell without substantial decrease in the static noise margin, which is the operational margin of the memory cell. To this end, a voltage Vdd′ higher than a power supply voltage Vdd of a power supply line for peripheral circuits is supplied from a power supply line for memory cells as a power supply voltage for memory cells. Since the conductance of driver MOS transistors is in-creased, the threshold voltage of the MOS transistors within the memory cells can be reduced without reducing the static noise margin. Further the ratio of width between the driver MOS transistor and a transfer MOS transistor can be set to 1, thereby allowing a reduction in the memory cell area.

    摘要翻译： 使用用于低电压操作的SRAM存储单元的存储器被设计为降低构成存储器单元的MOS晶体管的阈值，而不会显着降低静态噪声容限，这是存储单元的操作余量。 为此，作为存储单元的电源电压，从用于存储单元的电源线提供高于外围电路用电源线的电源电压Vdd的电压Vdd'。 由于驱动器MOS晶体管的电导被增加，所以可以在不降低静态噪声容限的情况下减小存储单元内的MOS晶体管的阈值电压。 此外，可以将驱动器MOS晶体管和转移MOS晶体管之间的宽度比设置为1，从而允许存储单元区域的减小。

    Semiconductor memory device with memory cells operated by boosted voltage
    28.
    发明授权
    Semiconductor memory device with memory cells operated by boosted voltage 有权
    具有由升压电压工作的存储单元的半导体存储器件

    公开(公告)号：US06795332B2

    公开(公告)日：2004-09-21

    申请号：US10163310

    申请日：2002-06-07

    申请人： Masanao Yamaoka ,  Kenichi Osada ,  Koichiro Ishibashi

    发明人： Masanao Yamaoka ,  Kenichi Osada ,  Koichiro Ishibashi

    IPC分类号： G11C1100

    CPC分类号： G11C11/417 ,  G11C11/412 ,  Y10S257/903

    摘要： A memory using an SRAM memory cell intended for low-voltage operation is designed to decrease the threshold value of MOB transistors constituting the memory cell without substantial decrease in the static noise margin, which is the operational margin of the memory cell. To this end, a voltage Vdd′ higher than a power supply voltage Vdd of a power supply line for peripheral circuits is supplied from a power supply line for memory cells as a power supply voltage for memory cells. Since the conductance of driver MOB transistors is in-creased, the threshold voltage of the MOB transistors within the memory cells can be reduced without reducing the static noise margin. Further the ratio of width between the driver MOS transistor and a transfer MOB transistor can be set to 1, thereby allowing a reduction in the memory cell area.

    摘要翻译： 使用用于低电压操作的SRAM存储单元的存储器被设计为降低构成存储器单元的MOB晶体管的阈值，而不会显着降低静态噪声容限，这是存储单元的操作余量。 为此，作为存储单元的电源电压，从用于存储单元的电源线提供高于外围电路用电源线的电源电压Vdd的电压Vdd'。 由于驱动器MOB晶体管的电导被增加，所以可以减小存储单元内的MOB晶体管的阈值电压，而不会降低静态噪声容限。 此外，可以将驱动器MOS晶体管和转移MOB晶体管之间的宽度比设置为1，从而允许存储单元区域的减小。

    Semiconductor memory device with memory cells operated by boosted voltage
    30.
    发明授权
    Semiconductor memory device with memory cells operated by boosted voltage 有权
    具有由升压电压工作的存储单元的半导体存储器件

    公开(公告)号：US07589993B2

    公开(公告)日：2009-09-15

    申请号：US12133343

    申请日：2008-06-04

    申请人： Masanao Yamaoka ,  Kenichi Osada ,  Koichiro Ishibashi

    发明人： Masanao Yamaoka ,  Kenichi Osada ,  Koichiro Ishibashi

    IPC分类号： G11C11/00

    CPC分类号： G11C11/417 ,  G11C11/412 ,  Y10S257/903

    摘要： A memory using an SRAM memory cell intended for low-voltage operation is designed to decrease the threshold value of MOS transistors constituting the memory cell without substantial decrease in the static noise margin, which is the operational margin of the memory cell. To this end, a voltage Vdd′ higher than a power supply voltage Vdd of a power supply line for peripheral circuits is supplied from a power supply line for memory cells as a power supply voltage for memory cells. Since the conductance of driver MOS transistors is in-creased, the threshold voltage of the MOS transistors within the memory cells can be reduced without reducing the static noise margin. Further the ratio of width between the driver MOS transistor and a transfer MOS transistor can be set to 1, thereby allowing a reduction in the memory cell area.

    摘要翻译： 使用用于低电压操作的SRAM存储单元的存储器被设计为降低构成存储器单元的MOS晶体管的阈值，而不会显着降低静态噪声容限，这是存储单元的操作余量。 为此，作为存储单元的电源电压，从用于存储单元的电源线提供高于外围电路用电源线的电源电压Vdd的电压Vdd'。 由于驱动器MOS晶体管的电导被增加，所以可以在不降低静态噪声容限的情况下减小存储单元内的MOS晶体管的阈值电压。 此外，可以将驱动器MOS晶体管和转移MOS晶体管之间的宽度比设置为1，从而允许存储单元区域的减小。