公开(公告)号：US06366320B1

公开(公告)日：2002-04-02

申请号：US08987131

申请日：1997-12-08

Applicant: Rajendran Nair ,  Mark A. Beiley ,  Morteza Afghahi

Inventor： Rajendran Nair ,  Mark A. Beiley ,  Morteza Afghahi

IPC: H04N5335

CPC classification number: H04N5/3575 ,  H04N5/37213 ,  H04N5/374

Abstract: A semiconductor circuit having an analog storage array, a sense amplifier array in which each sense amp cell generates a differential signal pair in response to receiving first and second signals from the storage array. The circuit also includes an analog multiplexer through which a selected differential signal pair is driven into a signal processing pipe. In another embodiment, the sense amp cells each include an operational amplifier (opamp) pair configured as unity-gain closed loop amplifiers for driving the differential signal pair through the analog multiplexer. To improve settling time, the opamps are designed to provide an underdamped response while loaded with the analog transmission path through the analog mux. In yet another embodiment, each sense amp cell is activated one clock cycle before it is read. This allows speedy readout while transitioning from one cell to the next. Also, maintaining only two cells active at any given time during readout helps reduce power dissipation and substantially decouples power dissipation in the sense amp array from the size of the array. The embodiments of the invention can be used in different types of imaging systems, including for instance a digital camera.

Abstract translation: 一种具有模拟存储阵列的半导体电路，其中每个读出放大器单元响应于从存储阵列接收第一和第二信号而产生差分信号对的读出放大器阵列。 电路还包括模拟多路复用器，所选择的差分信号对被驱动到信号处理管中。 在另一个实施例中，感测放大器单元各自包括被配置为单位增益闭环放大器的运算放大器（运算放大器）对，用于通过模拟多路复用器驱动差分信号对。 为了改善建立时间，运算放大器被设计为在加载模拟多路复用器的模拟传输路径时提供欠阻抗响应。 在另一个实施例中，每个读出放大器单元在读取之前一个时钟周期被激活。 这允许在从一个单元过渡到下一个单元时快速读出。 此外，在读出期间，在任何给定时间只保持两个电池有效，从而有助于降低功耗，并将感测放大器阵列中的功耗大大地与阵列的尺寸相分离。 本发明的实施例可以用于不同类型的成像系统，包括例如数字照相机。

公开(公告)号：US06317154B2

公开(公告)日：2001-11-13

申请号：US09798406

申请日：2001-03-02

Applicant: Mark A. Beiley

Inventor： Mark A. Beiley

IPC: H04N5335

CPC classification number: H01L27/14643 ,  H01L27/14609 ,  H04N5/35527 ,  H04N5/3575 ,  H04N5/363 ,  H04N5/374 ,  H04N5/3745 ,  H04N5/37452

Abstract: A method for controlling a sensor to reduce reset noise is disclosed. The method including the steps of providing a reset command including a RESET signal and a first SAMPLE signal. The method also includes the steps of providing a read command including a first ADDRESS signal, a second SAMPLE signal, and a second ADDRESS signal. An apparatus including a system controller and a sensor controlled by the system controller is also disclosed. In one embodiment, the method and apparatus is provided for a sensor in a sensor array that is read-out in a pipelined fashion.

公开(公告)号：US5532622A

公开(公告)日：1996-07-02

申请号：US427396

申请日：1995-04-24

Applicant: Mark A. Beiley ,  John A. Fifield

Inventor： Mark A. Beiley ,  John A. Fifield

IPC: H03K5/1532 ,  H03K5/1534 ,  H03K19/096

CPC classification number: H03K5/1534

Abstract: A transition detector circuit produces an output pulse upon detection of a transition at any one of several input nodes using a single delay path so all input transitions produce the same output pulse width and with only one gate delay in the circuit. The circuit includes precharging means, coupled between the plurality of transitioning inputs and the output node, for charging the output node high. The precharging means comprises stacked field effect transistor (FET) devices, each having a gate connected to a respective one of the transitioning inputs. A first charging device for charging the output node high is coupled to the output node. A second charging device for discharging the output node low is coupled to the output node. A single delay means, coupled between the plurality of transitioning inputs and both the first and second charging devices, both turns off the first charging device and turns on the second charging device. Switching means, controlled by the plurality of transitioning inputs and coupled between the output node and the second charging device, disconnects the second charging device from the output node.

Abstract translation: 当检测到使用单个延迟路径的几个输入节点中的任何一个的转变时，转换检测器电路产生输出脉冲，因此所有输入转换产生相同的输出脉冲宽度，并且在电路中只有一个门延迟。 该电路包括耦合在多个转换输入和输出节点之间的预充电装置，用于对输出节点进行高电压充电。 预充电装置包括堆叠场效应晶体管（FET）器件，每个器件具有连接到相应的一个转换输入的栅极。 用于对输出节点充电的第一充电装置耦合到输出节点。 用于将输出节点放电的第二充电装置耦合到输出节点。 耦合在多个转换输入和第一和第二充电装置之间的单个延迟装置都关闭第一充电装置并打开第二充电装置。 由多个转换输入控制并耦合在输出节点和第二充电装置之间的开关装置将第二充电装置与输出节点断开。