公开(公告)号：US20240319761A1

公开(公告)日：2024-09-26

申请号：US18609073

申请日：2024-03-19

申请人： SAMSUNG ELECTRONICS CO., LTD.

发明人： Jaeyoung Lee ,  Byungsu Kim ,  Youngsan Kim ,  Jaegon Lee ,  Jaehoon Kim ,  Byeongho Lee ,  Jongjin Lee ,  Wookyeong Jeong

IPC分类号： G06F1/08 ,  H01L23/00 ,  H01L23/498 ,  H01L25/10 ,  H03K5/133 ,  H03K5/1534

CPC分类号： G06F1/08 ,  H03K5/133 ,  H01L23/49816 ,  H01L24/16 ,  H01L25/105 ,  H01L2224/16225 ,  H03K5/1534

摘要： A semiconductor device includes an intellectual property (IP) block configured to operate based on a first clock signal and a power voltage, a clock gating circuit configured to operate based on the power voltage, and generate the first clock signal by selectively performing clock gating on a second clock signal based on an enable signal, and a critical path monitor (CPM) configured to generate a digital code having a value, which varies according to a voltage drop of the power voltage, and activate the enable signal based on a comparison of the value of the digital code with a reference value.

公开(公告)号：US12068751B2

公开(公告)日：2024-08-20

申请号：US17852657

申请日：2022-06-29

申请人： Micron Technology, Inc.

发明人： Eric J. Stave ,  Tyler J. Gomm

IPC分类号： G11C11/4076 ,  G11C7/22 ,  H03K5/1534 ,  H03K5/156 ,  H03K19/21

CPC分类号： H03K5/1565 ,  G11C7/222 ,  H03K5/1534 ,  H03K19/21

摘要： A device includes a clock input circuit that when in operation receives a clock signal and transmits an internal clock signal based on the clock signal. The device also includes an internal clock generator coupled to the clock input circuit to receive the internal clock signal, wherein the internal clock generator comprises clock adjustment circuitry that when in operation generates a phase controlled internal clock signal having subsequent clock edges based upon a single clock edge of the internal clock signal, wherein the phase controlled internal clock signal comprises a first frequency as a multiple of a second frequency of the internal clock signal.

公开(公告)号：US11936382B2

公开(公告)日：2024-03-19

申请号：US16454596

申请日：2019-06-27

申请人： ATI TECHNOLOGIES ULC ,  ADVANCED MICRO DEVICES, INC.

发明人： Joyce Cheuk Wai Wong ,  Dragoljub Ignjatovic ,  Mikhail Rodionov ,  Ljubisa Bajic ,  Stephen V. Kosonocky ,  Steven J. Kommrusch

IPC分类号： H03L1/02 ,  H03K3/012 ,  H03K3/013 ,  H03K3/0231 ,  H03K3/03 ,  H03K5/15 ,  H03L5/00 ,  H03L7/085 ,  H03L7/099 ,  H03K5/1534

CPC分类号： H03K3/013 ,  H03K3/012 ,  H03K3/0231 ,  H03K3/03 ,  H03K5/1506 ,  H03K5/1508 ,  H03L1/02 ,  H03L5/00 ,  H03L7/085 ,  H03L7/0997 ,  H03K5/1534

摘要： An output clock frequency of an adaptive oscillator circuit changes in response to noise on an integrated circuit power supply line. The circuit features two identical delay lines which are separately connected to a regulated supply and a droopy supply. In response to noise on the droopy supply, the delay lines cause a change in the output clock frequency. The adaptive oscillator circuit slows down the output clock frequency when the droopy supply droops or falls below the regulated supply. The adaptive oscillator circuit clamps the output clock frequency at a level determined by the regulated supply when the droopy supply overshoots or swings above the regulated supply.

公开(公告)号：US20230336167A1

公开(公告)日：2023-10-19

申请号：US18212213

申请日：2023-06-21

申请人： Texas Instruments Incorporated

发明人： Gaetano Maria Walter Petrina ,  Michael Lueders ,  Nicola Rasera

IPC分类号： H03K5/1534 ,  H02M1/08 ,  H03K5/13 ,  H02M1/38

CPC分类号： H03K5/1534 ,  H02M1/08 ,  H03K5/13 ,  H02M1/38 ,  H03K2005/00078

摘要： Methods, apparatus, systems, and articles of manufacture are disclosed for cross-conduction detection. An example apparatus includes a cross detector circuit including a first transistor and a second transistor, the first transistor coupled to a load, a third transistor coupled to a first controlled delay circuit and the first transistor, a fourth transistor coupled to a second controlled delay circuit and to the third transistor at a phase node, and a control circuit coupled to the first controlled delay circuit, the second controlled delay circuit, and the load.

公开(公告)号：US20230238949A1

公开(公告)日：2023-07-27

申请号：US17584836

申请日：2022-01-26

申请人： Infineon Technologies AG

发明人： Sunanda Manjunath ,  Ketan Dewan ,  Juergen Schaefer

IPC分类号： H03K5/1534 ,  H03K5/08 ,  H03K5/05 ,  H03K7/08 ,  H03K19/17736

CPC分类号： H03K5/1534 ,  H03K5/086 ,  H03K5/05 ,  H03K7/08 ,  H03K19/17744 ,  H03K2005/00136

摘要： Some examples relate to a system including a pulse modulation (PM) circuit having a PM input and a PM output. The system also includes a load circuit having a load circuit input, and an I/O pad coupling the PM output to the load circuit input. An asymmetry detection circuit has a first asymmetry detection (AD) input coupled to the PM output via a first feedback path, a second AD input coupled to an output node of the I/O pad via a second feedback path, and an AD output coupled to the PM input of the pulse modulation circuit via a control path.

公开(公告)号：US20190172503A1

公开(公告)日：2019-06-06

申请号：US16151089

申请日：2018-10-03

申请人： RENESAS ELECTRONICS CORPORATION

发明人： Koichi TAKEDA ,  Takashi IWASE

IPC分类号： G11C5/14 ,  G11C8/14 ,  G11C8/08 ,  G11C7/10 ,  G11C8/18 ,  G11C8/10

CPC分类号： G11C5/14 ,  G11C7/1093 ,  G11C8/08 ,  G11C8/10 ,  G11C8/14 ,  G11C8/18 ,  H03K5/1534 ,  H03K19/0185 ,  H03K19/018521

摘要： According to an embodiment, a word line driver includes: a first inverter that is driven by a first power supply voltage and inverts and outputs a decode signal; a second inverter that is driven by a second power supply voltage and inverts and outputs the decode signal; a first PMOS transistor that is controlled to be turned on or off on the basis of an output signal of the second inverter; a first NMOS transistor that is controlled to be turned on or off on the basis of an output signal of the first inverter; and a second PMOS transistor that is provided between a power supply voltage terminal to which the second power supply voltage is supplied and the gate of the first PMOS transistor and is temporarily turned on in synchronization with falling of the decode signal.

公开(公告)号：US20190081622A1

公开(公告)日：2019-03-14

申请号：US16123266

申请日：2018-09-06

申请人： Toshiba Memory Corporation

发明人： Toshihiro YAGI

IPC分类号： H03K17/0412 ,  H03K19/0185 ,  H03K19/017 ,  H03K3/356

CPC分类号： H03K17/04123 ,  H03K3/356 ,  H03K3/35613 ,  H03K3/356182 ,  H03K5/133 ,  H03K5/1534 ,  H03K19/017 ,  H03K19/01721 ,  H03K19/0185 ,  H03K19/018521

摘要： According to one embodiment, in a level shift circuit, a first PMOS transistor is electrically connected at a gate to a first node to which a first signal having an amplitude to be a first power-supply potential is input, is electrically connected to a second node at a source, and is electrically connected at a drain to an output terminal from which a signal having an amplitude to be a second power-supply potential is output. The first NMOS transistor is electrically connected to the first node at a gate and is electrically connected to the output terminal at a drain. The second PMOS transistor is electrically connected to a node to be the second power-supply potential at a source, and is electrically connected to the second node at a drain. The potential adjusting circuit is electrically connected to at least the second node.

公开(公告)号：US20190001720A1

公开(公告)日：2019-01-03

申请号：US16023168

申请日：2018-06-29

申请人： Océ Holding B.V.

发明人： Werner Zollner ,  Michael Mayr ,  Guenter Gassner

IPC分类号： B41J29/38 ,  H03K5/1534

CPC分类号： B41J29/38 ,  B41J2/2132 ,  B41J2/2146 ,  B41J11/008 ,  H03K5/1534

摘要： Aspects of the disclosure relate to a method and a compensator via which the input edges of the encoder signal of an encoder may be transformed into a compensated encoder signal such that requirements with regard to a dot resolution of a printing device and with regard to a maximum activation frequency of the dot generators of the printing device are satisfied.

公开(公告)号：US20180323794A1

公开(公告)日：2018-11-08

申请号：US15774455

申请日：2016-11-04

申请人： Teledyne e2v Semiconductors SAS

发明人： Etienne BOUIN ,  Rémi LAUBE ,  Jérôme LIGOZAT ,  Marc STACKLER

IPC分类号： H03M1/06

CPC分类号： H03M1/0624 ,  H03K5/1534 ,  H03K2005/00267 ,  H03M1/1215

摘要： In an architecture for processing data comprising a control unit and converters CNj to be synchronized to an active front of a common reference clock CLK, the synchronizing method makes provision for the converters to be arranged in at least one series chain, and for a procedure for synchronizing the converters by propagating a synchronizing signal SYNC-m emitted by the control unit, said signal being retransmitted as output OUT by each converter, after resynchronization to a clock active front, to a synchronization input IN of a following converter in the chain. Each converter comprises a synchronization configuration register REG containing at least one polarity parameter Sel-edgej that sets the polarity of the reference-clock front for reliable detection of a synchronizing signal received via the input of the converter. A phase parameter Sel-shiftj furthermore allows the phase of the sampling clocks of n converting cores of the converters, working at a sampling frequency obtained by dividing by n the CLK reference-clock frequency, to be synchronized.

公开(公告)号：US20180253521A1

公开(公告)日：2018-09-06

申请号：US15560161

申请日：2017-02-24

申请人： Southeast University

发明人： Weiwei SHAN ,  Wentao DAI ,  Jun YANG ,  Longxing SHI

IPC分类号： G06F17/50

CPC分类号： G06F17/5045 ,  G06F17/5031 ,  G06F2217/84 ,  H03K5/1534 ,  H03K5/19

摘要： An online monitoring unit and a control circuit for ultra-wide voltage range applications are disclosed. Compared with a conventional online monitoring unit, the present invention eliminates the need to reserve delay units, replaces flip-flops in the conventional online monitoring unit with a latch, and uses a transition detector with fewer transistors than that of a shadow latch in the conventional online monitoring unit, thereby reducing the area and the power consumption of the online monitoring unit significantly and improving the energy efficiency of online monitoring techniques. In addition, in the ultra-wide voltage range applications, the time borrowing property of the latch adopted by the present invention can be utilized to prevent a timing error caused by PVT variations, thus enabling the minimization of timing margin and ensuring higher power efficiency. The present invention also discloses a control circuit for use with the online monitoring unit.