公开(公告)号：US07285480B1

公开(公告)日：2007-10-23

申请号：US11279063

申请日：2006-04-07

申请人： Rajiv V. Joshi ,  Louis C. Hsu ,  Oleg Gluschenkov

发明人： Rajiv V. Joshi ,  Louis C. Hsu ,  Oleg Gluschenkov

IPC分类号： H01L21/00

CPC分类号： H01L21/84 ,  H01L27/1203 ,  H01L29/78654

摘要： An Integrated Circuit (IC) chip that may be a bulk CMOS IC chip with silicon on insulator (SOI) Field Effect Transistors (FETs) and method of making the chip. The IC chip includes areas with pockets of buried insulator strata and FETs formed on the strata are SOI FETs. The SOI FETs may include Partially Depleted SOI (PD-SOI) FETs and Fully Depleted SOI (FD-SOI) FETs and the chip may include bulk FETs as well. The FETs are formed by contouring the surface of a wafer, conformally implanting oxygen to a uniform depth, and planarizing to remove the Buried OXide (BOX) in bulk FET regions.

摘要翻译： 一种集成电路（IC）芯片，其可以是具有绝缘体上硅（SOI）场效应晶体管（FET）和制造芯片的方法的体CMOS IC芯片。 IC芯片包括具有埋入绝缘体层的凹坑的区域，并且在层上形成的FET是SOI FET。 SOI FET可以包括部分耗尽的SOI（PD-SOI）FET和完全耗尽的SOI（FD-SOI）FET，并且芯片也可以包括体FET。 FET通过轮廓化晶片的表面，将氧气保形地均匀地注入到均匀的深度，并平坦化以去除体FET区域中的掩埋氧化物（BOX）来形成。

公开(公告)号：US06864540B1

公开(公告)日：2005-03-08

申请号：US10851530

申请日：2004-05-21

申请人： Rama Divakaruni ,  Louis C. Hsu ,  Rajiv V. Joshi ,  Carl J. Radens

发明人： Rama Divakaruni ,  Louis C. Hsu ,  Rajiv V. Joshi ,  Carl J. Radens

IPC分类号： H01L21/336 ,  H01L29/45 ,  H01L29/76 ,  H01L29/786

CPC分类号： H01L29/66553 ,  H01L29/458 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/66628 ,  H01L29/66772 ,  H01L29/7842 ,  H01L29/78618 ,  H01L29/78684

摘要： The invention includes a field effect transistor (FET) on an insulator layer, and integrated circuit (IC) on SOI chip including the FETs and a method of forming the IC. The FETs include a thin channel with raised source/drain (RSD) regions at each end on an insulator layer, e.g., on an ultra-thin silicon on insulator (SOI) chip. Isolation trenches at each end of the FETs, i.e., at the end of the RSD regions, isolate and define FET islands. Insulating sidewalls at each RSD region sandwich the FET gate between the RSD regions. The gate dielectric may be a high K dielectric. Salicide on the RSD regions and, optionally, on the gates reduce device resistances.

摘要翻译： 本发明包括在绝缘体层上的场效应晶体管（FET）和包括FET的SOI芯片上的集成电路（IC）以及形成IC的方法。 FET包括在绝缘体层上的每个端部（例如，在绝缘体上的超薄绝缘体（SOI））芯片上的源极/漏极（RSD）区域上升的薄沟道。 在FET的每个端部，即在RSD区域的末端处的隔离沟槽隔离并限定FET岛。 每个RSD区域的绝缘侧壁将RSD区域之间的FET栅极夹在中间。 栅极电介质可以是高K电介质。 RSD区域上和可选地在栅极上的杀菌剂降低了器件电阻。

公开(公告)号：US08105936B2

公开(公告)日：2012-01-31

申请号：US12173899

申请日：2008-07-16

申请人： Chih-Chao Yang ,  Louis C. Hsu ,  Rajiv V. Joshi

发明人： Chih-Chao Yang ,  Louis C. Hsu ,  Rajiv V. Joshi

IPC分类号： H01L21/4763

CPC分类号： H01L21/76834 ,  H01L21/76814 ,  H01L21/76826 ,  H01L21/76843 ,  H01L21/76844 ,  H01L21/76846

摘要： Solutions for forming dielectric interconnect structures are provided. Specifically, the present invention provides methods of forming a dielectric interconnect structure having a noble metal layer that is formed directly on a modified dielectric surface. In a typical embodiment, the modified dielectric surface is created by treating an exposed dielectric layer of the interconnect structure with a gaseous ion plasma. Under the present invention, the noble metal layer could be formed directly on an optional glue layer that is maintained only on vertical surfaces of any trench or via formed in the exposed dielectric layer. In addition, the noble metal layer may be provided along an interface between the via and an internal metal layer.

摘要翻译： 提供了用于形成电介质互连结构的解决方案。 具体而言，本发明提供了形成具有直接形成在改性电介质表面上的贵金属层的电介质互连结构的方法。 在典型的实施例中，通过用气态离子等离子体处理互连结构的暴露的电介质层来产生修饰的电介质表面。 在本发明中，贵金属层可以直接形成在只保留在暴露的介电层中形成的任何沟槽或通孔的垂直表面上的任选胶层上。 此外，贵金属层可以沿通孔和内部金属层之间的界面设置。

公开(公告)号：US07521760B2

公开(公告)日：2009-04-21

申请号：US11775607

申请日：2007-07-10

申请人： Rajiv V. Joshi ,  Louis C. Hsu ,  Oleg Gluschenkov

发明人： Rajiv V. Joshi ,  Louis C. Hsu ,  Oleg Gluschenkov

IPC分类号： H01L27/01 ,  H01L27/12 ,  H01L31/0392 ,  H01L29/00 ,  H01L47/00

CPC分类号： H01L21/84 ,  H01L27/1203 ,  H01L29/78654

摘要： An Integrated Circuit (IC) chip that may be a bulk CMOS IC chip with silicon on insulator (SOI) Field Effect Transistors (FETs) and method of making the chip. The IC chip includes areas with pockets of buried insulator strata and FETs formed on the strata are SOI FETs. The SOI FETs may include Partially Depleted SOI (PD-SOI) FETs and Fully Depleted SOI (FD-SOI) FETs and the chip may include bulk FETs as well. The FETs are formed by contouring the surface of a wafer, conformally implanting oxygen to a uniform depth, and planarizing to remove the Buried OXide (BOX) in bulk FET regions.

摘要翻译： 一种集成电路（IC）芯片，其可以是具有绝缘体上硅（SOI）场效应晶体管（FET）和制造芯片的方法的体CMOS IC芯片。 IC芯片包括具有埋入绝缘体层的凹坑的区域，并且在层上形成的FET是SOI FET。 SOI FET可以包括部分耗尽的SOI（PD-SOI）FET和完全耗尽的SOI（FD-SOI）FET，并且芯片也可以包括体FET。 FET通过轮廓化晶片的表面，将氧气保形地均匀地注入到均匀的深度，并平坦化以去除体FET区域中的掩埋氧化物（BOX）来形成。

公开(公告)号：US08767501B2

公开(公告)日：2014-07-01

申请号：US13550762

申请日：2012-07-17

申请人： Rajiv V. Joshi ,  Ajay N. Bhoj

发明人： Rajiv V. Joshi ,  Ajay N. Bhoj

IPC分类号： G11C8/10

CPC分类号： G06F12/0864 ,  G06F2212/1021 ,  G11C15/04

摘要： Associative index extended (AIX) caches can be functionally implemented through a reconfigurable decoder that employs programmable line decoding. The reconfigurable decoder features scalability in the number of lines, the number of index extension bits, and the number of banks. The reconfigurable decoder can switch between pure direct mapped (DM) mode and direct mapped-associative index extended (DM-AIX) mode of operation. For banked configurations, the reconfigurable decoder provides the ability to run some banks in DM mode and some other banks in DM-AIX mode. A cache employing this reconfigurable decoder can provide a comparable level of latency as a DM cache with minimal modifications to a DM cache circuitry of an additional logic circuit on a critical signal path, while providing low power operation at low area overhead with SA cache-like miss rates. Address masking and most-recently-used-save replacement policy can be employed with a single bit overhead per line.

摘要翻译： 关联索引扩展（AIX）缓存可以通过采用可编程线解码的可重构解码器进行功能实现。 可重配置解码器具有线路数量的可扩展性，索引扩展位的数量和存储体的数量。 可重构解码器可以在纯直接映射（DM）模式和直接映射关联索引扩展（DM-AIX）操作模式之间切换。 对于组合配置，可重构解码器能够以DM模式运行某些存储区，并以DM-AIX模式运行其他存储区。 采用该可重构解码器的高速缓存器可以提供与DM高速缓存相当的延迟水平，对关键信号路径上的附加逻辑电路的DM高速缓存电路进行最小修改，同时在低区域开销提供具有SA缓存类似的低功率操作 错过率。 地址掩码和最近使用的保存替换策略可以采用每行一个位开销。

公开(公告)号：US08578316B1

公开(公告)日：2013-11-05

申请号：US13607678

申请日：2012-09-08

申请人： Rajiv V. Joshi ,  Ajay N. Bhoj

发明人： Rajiv V. Joshi ,  Ajay N. Bhoj

IPC分类号： G06F17/50

CPC分类号： G06F17/5068 ,  G06F17/5018

摘要： A method of automatically generating structure files employing a full structure generator automated program is provided. An annotated device layout file is generated from a design layout by annotating the codes for design shapes with additional text representing the functionality of a physical structure associated with each design shape. Functioning individual semiconductor devices are identified from the annotated device layout file, and a circuit area including multiple interconnected semiconductor devices are identified. A front-end-of-line (FEOL) device structure file and a back-end-of-line (BEOL) device structure file are generated from layer by layer analysis of the components of the annotated device layout within the circuit area. Finite element meshes (FEMs) are generated for the FEOL and BEOL structure files and merged to provide a structure file that can be employed for simulation of semiconductor devices therein.

公开(公告)号：US20130289965A1

公开(公告)日：2013-10-31

申请号：US13457722

申请日：2012-04-27

申请人： Rajiv V. Joshi ,  Rouwaida N. Kanj ,  Keunwoo Kim

发明人： Rajiv V. Joshi ,  Rouwaida N. Kanj ,  Keunwoo Kim

IPC分类号： G06F17/50

CPC分类号： G06F17/5068 ,  G06F2217/10

摘要： A method for analyzing circuits includes identifying one or more device zones in a full device structure. The device zones provide areas of interest to be analyzed. A partial device is generated that representatively includes the one or more device zones. Analytical meshes of the partial device are reduced by employing physical characteristics of the full device structure. The partial device is simulated, using a processor, to obtain device output information in the areas of interest that is representative of the full device structure. Systems are also disclosed.

公开(公告)号：US20130289948A1

公开(公告)日：2013-10-31

申请号：US13611359

申请日：2012-09-12

申请人： Rajiv V. Joshi ,  Rouwaida N. Kanj ,  Keunwoo Kim

发明人： Rajiv V. Joshi ,  Rouwaida N. Kanj ,  Keunwoo Kim

IPC分类号： G06F17/50

CPC分类号： G06F17/5068 ,  G06F2217/10

摘要： A method for analyzing circuits includes identifying one or more device zones in a full device structure. The device zones provide areas of interest to be analyzed. A partial device is generated that representatively includes the one or more device zones. Analytical meshes of the partial device are reduced by employing physical characteristics of the full device structure. The partial device is simulated, using a processor, to obtain device output information in the areas of interest that is representative of the full device structure. Systems are also disclosed.

摘要翻译： 一种用于分析电路的方法包括识别完整设备结构中的一个或多个设备区域。 设备区域提供要分析的感兴趣区域。 生成代表性地包括一个或多个设备区域的部分设备。 通过采用整个装置结构的物理特性来减少部分装置的分析网格。 使用处理器来模拟部分设备，以获得代表整个设备结构的感兴趣区域中的设备输出信息。 还披露了系统。

公开(公告)号：US20130042217A1

公开(公告)日：2013-02-14

申请号：US13205186

申请日：2011-08-08

申请人： Fook-Luen HENG ,  Rajiv V. Joshi ,  Alexey Y. Lvov ,  Xiaoping Tang

发明人： Fook-Luen HENG ,  Rajiv V. Joshi ,  Alexey Y. Lvov ,  Xiaoping Tang

IPC分类号： G06F17/50

CPC分类号： G06F17/5068

摘要： Methods and systems for migrating circuit layouts. A floorplan layout is built for a target circuit using a subset of constraints that characterize a layout structure of an original circuit. Shape-constraint-based scaling is used on the floorplan layout by scaling parts of the floorplan layout in accordance with a plurality of different scaling ratios such that portions of the floorplan layout are concurrently scaled with the plurality of different scaling ratios. Cells are placed at locations defined by the floorplan layout. The floorplan layout is checked with shape-constraint-based legalization using all of the constraints to produce a migrated layout.

摘要翻译： 迁移电路布局的方法和系统。 使用表征原始电路的布局结构的约束子集为目标电路构建平面图布局。 通过根据多个不同的缩放比例缩放平面图布局的部分，使得平面图布局的部分与多个不同的缩放比同时缩放，从而在平面图布局上使用基于形状约束的缩放。 细胞被放置在由平面图布局定义的位置处。 使用所有约束来生成迁移的布局，使用基于形状约束的合法化来检查平面图布局。

公开(公告)号：US08214777B2

公开(公告)日：2012-07-03

申请号：US12419377

申请日：2009-04-07

申请人： Rajiv V. Joshi ,  Rouwaida N. Kanj ,  Jente B. Kuang ,  Sani R. Nassif

发明人： Rajiv V. Joshi ,  Rouwaida N. Kanj ,  Jente B. Kuang ,  Sani R. Nassif

IPC分类号： G06F17/50

CPC分类号： G01R31/025 ,  G11C29/006 ,  G11C29/028 ,  G11C29/50 ,  G11C2029/5006 ,  G11C2029/5602

摘要： A leakage current monitor circuit provides an accurate statistically representative analog of true off-state leakage current in a digital circuit integrated on a die. At least one N-type transistor and at least one P-type transistor separate from the digital circuit are sized to represent the total area of the corresponding type transistors in the digital circuit. The gates of the N-type transistor and P-type transistors are set to voltages according to the corresponding off-state logic levels of the digital circuit. The N-type and P-type transistors form a portion of corresponding current mirror circuits, which can provide outputs to a leakage current monitor and/or a control circuit such as a comparator that determines when leakage current for the N-type or P-type devices has exceeded a threshold. The output of the measurement/control circuit can be used to determine a temperature of and/or control operation of the digital circuit or the system environment of the integrated circuit.

摘要翻译： 泄漏电流监测电路在集成在管芯上的数字电路中提供精确的统计代表性的真实截止漏电流的模拟。 与数字电路分离的至少一个N型晶体管和至少一个P型晶体管的尺寸被设计为表示数字电路中相应类型晶体管的总面积。 N型晶体管和P型晶体管的栅极根据数字电路的对应截止状态逻辑电平设置为电压。 N型和P型晶体管形成对应的电流镜电路的一部分，其可以向泄漏电流监视器和/或诸如比较器的控制电路提供输出，所述比较器确定N型或P-型晶体管的漏电流， 类型设备已超过阈值。 测量/控制电路的输出可用于确定集成电路的数字电路或系统环境的温度和/或控制操作。