公开(公告)号：US20060179286A1

公开(公告)日：2006-08-10

申请号：US11054201

申请日：2005-02-09

申请人： Juergen Haess ,  Michael Kroener ,  Dung Nguyen ,  Eric Schwarz ,  Son Dao-Trong ,  Raymond Yeung

发明人： Juergen Haess ,  Michael Kroener ,  Dung Nguyen ,  Eric Schwarz ,  Son Dao-Trong ,  Raymond Yeung

IPC分类号： G06F9/44

CPC分类号： G06F9/3867 ,  G06F9/3838

摘要： A system for performing limited out-of order execution of floating point loads. The system includes a plurality of stages making up a pipeline, the stages including an early stage. The system also includes a mechanism for inputting an arithmetic instruction into the pipeline, the arithmetic instruction including a result address. The mechanism also determines if the arithmetic instruction causes a write after write (WAW) condition to occur before writing a result of the arithmetic instruction to the result address. The determining includes comparing the result address to a load address associated with a load instruction subsequent to the arithmetic instruction in the pipeline. The load data associated with the load instruction was written to the load address in the early stage of the pipeline. A WAW condition occurs if the result address is equal to the load address. Writing a result of the arithmetic instruction is suppressed in response to the WAW condition occurring.

摘要翻译： 用于执行浮点负载有限次序执行的系统。 该系统包括构成管道的多个阶段，这些阶段包括早期阶段。 该系统还包括用于将算术指令输入流水线的机构，算术指令包括结果地址。 该机制还确定在将算术指令的结果写入结果地址之前，算术指令是否在写入（WAW）条件之后发生写入。 确定包括将结果地址与在流水线中的算术指令之后的加载指令相关联的加载地址进行比较。 与加载指令相关联的加载数据在管道的早期阶段被写入加载地址。 如果结果地址等于加载地址，则会发生WAW条件。 响应于发生的WAW状态，写入算术指令的结果被抑制。

公开(公告)号：US20060179103A1

公开(公告)日：2006-08-10

申请号：US11054687

申请日：2005-02-09

申请人： Steven Carlough ,  Wilhelm Haller ,  Wen Li ,  Eric Schwarz

发明人： Steven Carlough ,  Wilhelm Haller ,  Wen Li ,  Eric Schwarz

IPC分类号： G06F7/50

CPC分类号： G06F7/4912 ,  G06F7/483 ,  G06F7/507

摘要： A system for performing decimal floating point addition. The system includes input registers for inputting a first and second operand for an addition operation. The system also includes a plurality of adder blocks, each calculating a sum of one or more corresponding digits from the first operand and the second operand. Output from each of the adder blocks includes the sum of the corresponding digits and a carry out indicator for the corresponding digits. The calculating is performed during a first clock cycle. The system also includes an intermediate result register for storing the sums of the corresponding digits output from each of the plurality of adder blocks, the storing during the first clock cycle. The system further includes a carry chain for storing the carry out indicator output from each of the plurality of adder blocks, the storing occurring during the first clock cycle. The system further includes an incrementer for adding one to each of the sums stored in the intermediate result register, the incrementing occurring during a second clock cycle. In addition, a mechanism is provided for selecting between each of the sums and the sums incremented by one. The input to the mechanism includes the carry chain. The output includes the final sum of the first operand and the second operand. The selecting occurs during the second clock cycle.

公开(公告)号：US20060179098A1

公开(公告)日：2006-08-10

申请号：US11054234

申请日：2005-02-09

申请人： Michael Kelly ,  Wen Li ,  Eric Schwarz ,  Wai Wong

发明人： Michael Kelly ,  Wen Li ,  Eric Schwarz ,  Wai Wong

IPC分类号： G06F7/38

CPC分类号： G06F7/74 ,  G06F7/491 ,  G06F2207/4911

摘要： A method for leading zero detection. The method includes receiving DPD encoded data representing a three digit BCD number and determining directly from the DPD encoded data if the BCD number represented by the DPD encoded data contains at least one leading zero digit. A group one switch is set to zero if it was determined that the BCD number represented by the DPD encoded data contains at least one leading zero digit and set to one otherwise. The method also includes determining directly from the DPD encoded data if the BCD number represented by the DPD encoded data contains at least two leading zero digits. A group two switch is set to zero if it was determined that the BCD number represented by the DPD encoded data contains at least two leading zero digits and set to one otherwise. The method further includes determining directly from the DPD encoded data if the BCD number represented by the DPD encoded data contains three leading zero digits. A group three switch is set to zero if was determined that the BCD number represented by the DPD encoded data contains three leading zero digits and set to one otherwise.

摘要翻译： 一种引导零检测的方法。 如果由DPD编码数据表示的BCD数字包含至少一个前导零数字，则该方法包括接收表示三位BCD号码的DPD编码数据，并直接从DPD编码数据确定。 如果确定由DPD编码数据表示的BCD数字包含至少一个前导零数字并且另外设置为一个，则将一组开关设置为零。 如果由DPD编码数据表示的BCD数字包含至少两个前导零数字，则该方法还包括直接从DPD编码数据确定。 如果确定由DPD编码数据表示的BCD数字包含至少两个前导零数字并且另外设置为一个，则组二开关被设置为零。 如果由DPD编码数据表示的BCD数字包含三个前导零数字，则该方法还包括直接从DPD编码数据确定。 如果确定由DPD编码数据表示的BCD数字包含三个前导零数字并且另外设置为一个，则组三开关被设置为零。

公开(公告)号：US20060179097A1

公开(公告)日：2006-08-10

申请号：US11054110

申请日：2005-02-09

申请人： Bruce Fleischer ,  Juergen Haess ,  Michael Kroener ,  Martin Schmookler ,  Eric Schwarz ,  Son Dao-Trong

发明人： Bruce Fleischer ,  Juergen Haess ,  Michael Kroener ,  Martin Schmookler ,  Eric Schwarz ,  Son Dao-Trong

IPC分类号： G06F7/38

CPC分类号： G06F7/483 ,  G06F7/499 ,  G06F7/49936 ,  G06F7/49947 ,  G06F7/5443 ,  G06F2207/382

摘要： A system for performing floating point arithmetic operations including an input register adapted for receiving an operand. The system also includes a mechanism for performing a shift or masking operation in response to determining that the operand is in an un-normalized format. The system also includes instructions for performing single precision incrementing of the operand in response to determining that the operand is single precision, that the operand requires the incrementing based on the results of a previous operation and that the previous operation did not perform the incrementing. The operand was created in the previous operation. The system further includes instructions for performing double precision incrementing of the operand in response to determining that the operand is double precision, that the operand requires the incrementing based on the results of the previous operation and that the previous operation did not perform the incrementing.

摘要翻译： 一种用于执行浮点算术运算的系统，包括适于接收操作数的输入寄存器。 该系统还包括响应于确定操作数处于非归一化格式而执行移位或掩蔽操作的机制。 该系统还包括用于响应于确定操作数是单一精度来执行操作数的单精度递增的指令，操作数需要基于先前操作的结果而增加，并且先前的操作未执行递增。 操作数是在以前的操作中创建的。 该系统还包括响应于确定操作数是双精度来执行操作数的双精度递增的指令，操作数需要基于先前操作的结果而增加，并且先前的操作不执行递增。

公开(公告)号：US20060179096A1

公开(公告)日：2006-08-10

申请号：US11055232

申请日：2005-02-10

申请人： Bruce Fleischer ,  Juergen Haess ,  Michael Kroener ,  Robert Montoye ,  Martin Schmookler ,  Eric Schwarz ,  Son Dao-Trong

发明人： Bruce Fleischer ,  Juergen Haess ,  Michael Kroener ,  Robert Montoye ,  Martin Schmookler ,  Eric Schwarz ,  Son Dao-Trong

IPC分类号： G06F7/38

CPC分类号： G06F7/483 ,  G06F7/49947 ,  G06F7/5443

摘要： A system for performing floating point arithmetic operations including an input register adapted for receiving an operand. The system also includes computer instructions for performing single precision incrementing of the operand in response to determining that the operand is single precision, that the operand requires the incrementing based on the results of a previous operation and that the previous operation did not perform the incrementing. The operand was created in the previous operation. The system further includes instructions for performing double precision incrementing of the operand in response to determining that the operand is double precision, that the operand requires the incrementing based on the results of the previous operation and that the previous operation did not perform the incrementing.

摘要翻译： 一种用于执行浮点算术运算的系统，包括适于接收操作数的输入寄存器。 该系统还包括用于响应于确定操作数是单精度来执行操作数的单精度递增的计算机指令，操作数基于先前操作的结果需要增加，并且先前的操作未执行递增。 操作数是在以前的操作中创建的。 该系统还包括响应于确定操作数是双精度来执行操作数的双精度递增的指令，操作数需要基于先前操作的结果而增加，并且先前的操作不执行递增。

公开(公告)号：US20060047738A1

公开(公告)日：2006-03-02

申请号：US10930129

申请日：2004-08-31

申请人： Eric Schwarz ,  Martin Schmookler

发明人： Eric Schwarz ,  Martin Schmookler

IPC分类号： G06F7/38

CPC分类号： G06F7/49947 ,  G06F7/491 ,  G06F7/49963

摘要： A method of processing data employs a new rounding mode called “round for reround” on the original arithmetic instruction in the hardware precision, and then 2) invoking an instruction which specifies a variable rounding precision and possibly explicitly sets the rounding mode which we have called the ReRound instruction. The precise result of the arithmetic operation is first truncated to the hardware format precision “p”, forming an intermediate result. If only zeros are dropped during truncation, then the intermediate result is equal to the precise result, and this result is said to be “exact”, otherwise, it is “inexact”. When the intermediate result is inexact and its least significant digit is either zero or five, then that digit is incremented to one or six respectively forming the rounded result. Thus, when the least significant digit of a rounded result is zero or five the result could be construed to be exact or exactly halfway between two machine representations if it were later rounded to one less digit of precision. For all other values, it is obvious that the result is inexact and not halfway between two machine representations for later roundings to fewer than “p” digits of precision. A nice mathematical property of this rounding mode is that results stay ordered and in a hardware implementation it is guaranteed that the incrementation of the least significant digit does not cause a carry into the next digit of the result.

摘要翻译： 处理数据的方法采用在硬件精度上对原始算术指令称为“round for reround”的新的舍入模式，然后2）调用指定变量舍入精度的指令，并可能明确地设置我们称之为舍入模式 ReRound指令。 算术运算的精确结果首先被截断为硬件格式精度“p”，形成中间结果。 如果在截断期间仅删除零，则中间结果等于精确结果，并且该结果被称为“精确”，否则为“不精确”。 当中间结果不精确，其最低有效位为零或五时，则该数字分别增加到一个或六个，分别形成舍入结果。 因此，当舍入结果的最低有效数字为零或五时，如果结果被稍后舍入为一个较小的精度数字，则结果可以被解释为两个机器表示之间的精确或准确的中间。 对于所有其他值，很明显，结果是不精确的，而不是两个机器表示之间的中间，以便稍后的舍入少于“p”位精度。 这种舍入模式的一个很好的数学属性是结果保持有序，并且在硬件实现中，保证最低有效位的递增不会导致结果的下一个数字的进位。

公开(公告)号：US08082467B2

公开(公告)日：2011-12-20

申请号：US12645771

申请日：2009-12-23

申请人： Gregory W. Alexander ,  Fadi Busaba ,  David A. Schroter ,  Eric Schwarz ,  Brian W. Thompto ,  Wesley J. Ward, III

发明人： Gregory W. Alexander ,  Fadi Busaba ,  David A. Schroter ,  Eric Schwarz ,  Brian W. Thompto ,  Wesley J. Ward, III

IPC分类号： G06F11/00

CPC分类号： G06F9/30145 ,  G06F9/30189 ,  G06F9/3853 ,  G06F9/3861 ,  G06F9/3867 ,  G06F11/004 ,  G06F11/0721 ,  G06F11/0724 ,  G06F11/0751 ,  G06F11/0793

摘要： A novel system and method for working around a processing flaw in a processor is disclosed. At least one instruction is fetched from a memory location. The instruction is decoded. A set of opcode compare logic, associated with an instruction decode unit and/or a set of global completion table, is used for an opcode compare operation. The compare operation compares the instruction and a set of values within at least one opcode compare register in response to the decoding. The instruction is marked with a pattern based on the opcode compare operation. The pattern indicates that the instruction is associated with a processing flaw. The pattern is separate and distinct from opcode information within the instruction that is utilized by the set of opcode compare logic during the opcode compare operation.

摘要翻译： 公开了一种用于处理处理器中的处理缺陷的新颖系统和方法。 从存储器位置获取至少一个指令。 该指令被解码。 与指令解码单元和/或一组全局完成表相关联的一组操作码比较逻辑被用于操作码比较操作。 响应于解码，比较操作将指令和至少一个操作码比较寄存器中的一组值进行比较。 该指令用基于操作码比较操作的模式标记。 该模式表示该指令与处理缺陷相关联。 该模式与操作码比较操作期间的一组操作码比较逻辑所使用的指令内的操作码信息分开且不同。

公开(公告)号：US20110153991A1

公开(公告)日：2011-06-23

申请号：US12645716

申请日：2009-12-23

申请人： FADI BUSABA ,  Brian Curran ,  Lee Eisen ,  Christian Jacobi ,  David A. Schroter ,  Eric Schwarz

发明人： FADI BUSABA ,  Brian Curran ,  Lee Eisen ,  Christian Jacobi ,  David A. Schroter ,  Eric Schwarz

IPC分类号： G06F9/312 ,  G06F9/30

CPC分类号： G06F9/3001 ,  G06F9/30043 ,  G06F9/3017 ,  G06F9/3836 ,  G06F9/3867

摘要： A system and method for issuing a processor instruction to multiple processing sections arranged in an out-of-order processing pipeline architecture. The multiple processing sections include a first execution unit with a pipeline length and a second execution unit operating upon data produced by the first execution unit. An instruction issue unit accepts a complex instruction that is cracked into respective micro-ops for the first execution unit and the second execution unit. The instruction issue unit issues the first micro-op to the first execution unit to produce intermediate data. The instruction issue unit then delays for a time period corresponding to the processing pipeline length of the first execution unit. After the delay, a second micro-op is issued to the second execution unit.

摘要翻译： 一种用于向处理流水线结构排列的多个处理部分发出处理器指令的系统和方法。 多个处理部分包括具有流水线长度的第一执行单元和对由第一执行单元产生的数据进行操作的第二执行单元。 指令发布单元接受对于第一执行单元和第二执行单元破解为相应微操作的复杂指令。 指令发布单元向第一执行单元发出第一微操作以产生中间数据。 然后，指令发布单元延迟与第一执行单元的处理流水线长度对应的时间段。 在延迟之后，向第二执行单元发出第二个微操作。

公开(公告)号：US20060179100A1

公开(公告)日：2006-08-10

申请号：US11054686

申请日：2005-02-09

申请人： Juergen Haess ,  Michael Kroener ,  Dung Nguyen ,  Lawrence Powell ,  Eric Schwarz ,  Son Dao-Trong ,  Raymond Yeung

发明人： Juergen Haess ,  Michael Kroener ,  Dung Nguyen ,  Lawrence Powell ,  Eric Schwarz ,  Son Dao-Trong ,  Raymond Yeung

IPC分类号： G06F7/38

CPC分类号： G06F9/3826 ,  G06F9/30014 ,  G06F9/3824 ,  G06F9/3838 ,  G06F9/3885

摘要： A system for performing floating point arithmetic operations including a plurality of stages making up a pipeline, the stages including a first stage and a last stage. The system also includes a register file adapted for receiving a store instruction for input to the pipeline, where the data associated with the store instruction is dependent on a previous operation still in the pipeline. The system further includes a store register adapted for outputting the data associated with the store instruction to memory and a control unit having instructions. The instructions are directed to inputting the store instruction into the pipeline and to providing a path for forwarding the data associated with the store instruction from the last stage in the pipeline to the store register for use by the store instruction if the previous operation immediately precedes the store operation in the pipeline and if there is a data type match between the store instruction and the previous operation. In addition, the instructions are directed to inputting the store instruction into the pipeline and to providing a path for forwarding the data associated with the store instruction from the first stage in the pipeline to the store register for use by the store instruction if the previous operation precedes the store operation by one or more stage in the pipeline and if there is a data type match between the store instruction and the previous operation.

摘要翻译： 一种用于执行浮点算术运算的系统，包括构成流水线的多个级，所述级包括第一级和最后级。 该系统还包括适于接收用于输入到流水线的存储指令的寄存器文件，其中与存储指令相关联的数据依赖于仍在流水线中的先前操作。 该系统还包括适于将与存储指令相关联的数据输出到存储器的存储寄存器和具有指令的控制单元。 这些指令旨在将存储指令输入到流水线中，并且提供一个路径，用于将与流水线中的最后一级相关联的存储指令的数据转发到存储寄存器以供存储指令使用，如果先前的操作紧接在 存储操作在流水线中，并且存储指令与先前操作之间存在数据类型匹配。 此外，该指令旨在将存储指令输入到流水线中，并且提供用于将与流水线中的第一级相关联的存储指令的数据转发到存储寄存器以供存储指令使用的路径，如果先前的操作 在存储操作之前在流水线中的一个或多个阶段，以及存储指令和先前操作之间是否存在数据类型匹配。

公开(公告)号：US20060179091A1

公开(公告)日：2006-08-10

申请号：US11054233

申请日：2005-02-09

申请人： Steven Carlough ,  Bruce Fleischer ,  Wen Li ,  Eric Schwarz

发明人： Steven Carlough ,  Bruce Fleischer ,  Wen Li ,  Eric Schwarz

IPC分类号： G06F7/00

CPC分类号： H03M7/12

摘要： A method for converting from binary to decimal. The method includes receiving a binary coded decimal (BCD) number made up of one or more sets of three digits. A running sum and a running carry are set to zero. The following steps are performed for each set of three digits in the BCD number in order from the set of three digits containing the three most significant digits of the BCD number to the set of three digits containing the three least significant digits of the BCD number. The steps include: creating six partial products based on the set of three digits, the running sum and the running carry; combining the six partial products into two partial products; and storing the two partial products in the running sum and the running carry. After the loop has been performed for each set of three digits in the BCD number, the running sum and the running carry are combined into a final binary result.

摘要翻译： 一种从二进制转换为十进制的方法。 该方法包括接收由一个或多个三位数字组成的二进制编码十进制（BCD）号码。 运行总和和运行进位设置为零。 对于BCD号码中的每一组三位数字，按照从包含BCD号码三个最高有效数字的三位数字到包含BCD号码三个最低有效位数字的三位数组的顺序执行以下步骤。 步骤包括：根据三位数字，运行总和和运行进位创建六个部分产品; 将六部分产品合并成两部分产品; 并将两个部分乘积存储在运行和运行中。 在对BCD号码中的每组三位数进行了循环之后，运行总和和运行进位被组合成最终的二进制结果。