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    GLITCH FREE DYNAMIC ELEMENT MATCHING SCHEME
    4.
    发明申请
    GLITCH FREE DYNAMIC ELEMENT MATCHING SCHEME 有权
    免费动态元素匹配方案

    公开(公告)号：US20120176264A1

    公开(公告)日：2012-07-12

    申请号：US13422833

    申请日：2012-03-16

    Applicant: Rakhel Kumar PARIDA ,  Ankur BAL ,  Anil KUMAR ,  Anupam JAIN

    Inventor： Rakhel Kumar PARIDA ,  Ankur BAL ,  Anil KUMAR ,  Anupam JAIN

    IPC: H03M1/66

    CPC classification number: H03M7/12 ,  H03M1/0665 ,  H03M1/0673 ,  H03M1/74 ,  H03M7/14

    Abstract: A dynamic element matching (DEM) scheme is implemented in a crawling code generator for converting a b-bit binary input code into a (2b−1)-bit digital output code. A random generator determines for every conversion step a direction. A decimal difference between the current and previous binary input is calculated. The new crawling output code is determined based on the previous crawling output code, the direction and the decimal difference. The DEM scheme is used in a digital-to-analog converter such that the crawling output code switches digital-to-analog converting elements that output analog signals that are then summed to be the final analog signal.

    Abstract translation: 用于将b位二进制输入代码转换为（2b-1）位数字输出代码的爬行码生成器中实现动态元素匹配（DEM）方案。 随机生成器确定每个转换步骤一个方向。 计算当前和前一个二进制输入之间的十进制差值。 新的爬行输出代码基于先前的爬行输出代码，方向和小数差来确定。 DEM方案用于数模转换器，使得爬行输出码切换输出模拟信号的数模转换元件，然后将模拟信号相加为最终的模拟信号。

    Glitch free dynamic element matching scheme
    5.
    发明授权
    Glitch free dynamic element matching scheme 有权
    无毛刺动态元素匹配方案

    公开(公告)号：US08159381B2

    公开(公告)日：2012-04-17

    申请号：US12842311

    申请日：2010-07-23

    Applicant: Rakhel Kumar Parida ,  Ankur Bal ,  Anil Kumar ,  Anupam Jain

    Inventor： Rakhel Kumar Parida ,  Ankur Bal ,  Anil Kumar ,  Anupam Jain

    IPC: H03M1/66

    CPC classification number: H03M7/12 ,  H03M1/0665 ,  H03M1/0673 ,  H03M1/74 ,  H03M7/14

    Abstract: A dynamic element matching (DEM) scheme is implemented in a crawling code generator for converting a b-bit binary input code into a (2b−1)-bit digital output code. A random generator determines for every conversion step a direction. A decimal difference between the current and previous binary input is calculated. The new crawling output code is determined based on the previous crawling output code, the direction and the decimal difference. The DEM scheme is used in a digital-to-analog converter such that the crawling output code switches digital-to-analog converting elements that output analog signals that are then summed to be the final analog signal.

    Abstract translation: 用于将b位二进制输入代码转换为（2b-1）位数字输出代码的爬行码生成器中实现动态元素匹配（DEM）方案。 随机生成器确定每个转换步骤一个方向。 计算当前和前一个二进制输入之间的十进制差值。 新的爬行输出代码基于先前的爬行输出代码，方向和小数差来确定。 DEM方案用于数模转换器，使得爬行输出码切换输出模拟信号的数模转换元件，然后将模拟信号相加为最终的模拟信号。

    System and method for performing decimal to binary conversion
    6.
    发明授权
    System and method for performing decimal to binary conversion 有权
    用于执行十进制到二进制转换的系统和方法

    公开(公告)号：US07660838B2

    公开(公告)日：2010-02-09

    申请号：US11054233

    申请日：2005-02-09

    Applicant: Steven R. Carlough ,  Bruce M. Fleischer ,  Wen H. Li ,  Eric M. Schwarz

    Inventor： Steven R. Carlough ,  Bruce M. Fleischer ,  Wen H. Li ,  Eric M. Schwarz

    IPC: G06F15/00

    CPC classification number: H03M7/12

    Abstract: A method for converting from decimal to binary including receiving a binary coded decimal (BCD) number made up of one or more sets of three digits. A running sum and a running carry are set to zero. A process is performed for each set of three digits in the BCD number in order from the set of three digits containing the three most significant digits of the BCD number to the digits containing the three least significant digits of the BCD number. The process includes: creating six partial products based on the set of three digits, the running sum and the running carry; combining the six partial products into two partial products; and storing the two partial products in the running sum and the running carry. The running sum and the running carry from each set of three digits are combined into a final binary result.

    Abstract translation: 一种从十进制转换为二进制的方法，包括接收一组三位数组成的二进制编码十进制（BCD）编号。 运行总和和运行进位设置为零。 对于BCD号码中的每一组三位数字，从包含BCD号码三个最高有效数字的三位数字组合到包含BCD号码的三个最低有效位数字的顺序执行一个处理。 该过程包括：根据三位数字，运行总和和运行进位创建六个部分乘积; 将六部分产品合并成两部分产品; 并将两个部分乘积存储在运行和运行中。 来自每组三位数的运行总和和运行进位被组合成最终的二进制结果。

    Method for converting the binary representation of a number in a signed binary representation
    7.
    发明申请
    Method for converting the binary representation of a number in a signed binary representation 失效
    用于转换有符号二进制表示中的数字的二进制表示的方法

    公开(公告)号：US20040215684A1

    公开(公告)日：2004-10-28

    申请号：US10312530

    申请日：2003-04-23

    Inventor： Marc Joye ,  Sung-Ming Yen

    IPC: G06F007/38

    CPC classification number: H03M7/12 ,  G06F7/5332

    Abstract: The invention concerns a method for converting in a signed binary representation (rnullm, rnull0) of a number r based on a left-to-right processing of bits of the binary representation (rnullm, rnull0) and enabling to obtain a representation equivalent to the so-called Reitwiesner representation. The use of such a conversion method with left-to-right arithmetic processing enables to improve their hardware implementation.

    Abstract translation: 本发明涉及一种用于基于二进制表示（r'm，r'0）的比特的从左到右处理而以数字r的有符号二进制表示（r'm，r'0）进行转换的方法，以及 使得能够获得与所谓的Reitwiesner表示相当的表示。 使用这种从左到右算术处理的转换方法能够改进其硬件实现。

    Decimal to binary coder/decoder
    8.
    发明授权
    Decimal to binary coder/decoder 有权
    十进制到二进制编码器/解码器

    公开(公告)号：US06437715B1

    公开(公告)日：2002-08-20

    申请号：US09932352

    申请日：2001-08-17

    Applicant: Michael Frederic Cowlishaw

    Inventor： Michael Frederic Cowlishaw

    IPC: H03M704

    CPC classification number: H03M7/12

    Abstract: A system and method are provided for encoding from decimal to binary and back again. The coding is based on representing 3 decimal digits as 10 binary bits and is a development of the Chen-Ho algorithm. This provides a storage efficiency of >99%, yet still allows decimal arithmetic to be readily performed. The decimal input is typically first converted to binary coded decimal (4 bits per decimal digit), before compression to 10 bits. Adopting the encoding of the present invention, if the leading (most significant) decimal digit is zero, then the first three bits of the binary output are zero; and if the first two decimal digits are zero, then the first six bits of the binary output are zero. Accordingly, the same coding can be flexibly used to code 2 decimal digits to 7 binary bits, and 1 decimal digit to 4 binary bits. This makes it particularly suitable for standard computer architectures which are based on a power of two (16-bit, 32-bit, 64-bit, etc), and therefore not directly divisible by 7 or by 10.

    Abstract translation: 提供了一种用于从十进制到二进制进行编码的系统和方法。 编码是以10位二进制位数表示3位十进制数，是Chen-Ho算法的开发。 这提供了> 99％的存储效率，但仍允许十进制算术容易地执行。 十进制输入通常首先转换为二进制编码十进制（每十进制数4位），然后再压缩为10位。 采用本发明的编码方式，如果前导（最高有效）十位数为零，则二进制输出的前三位为零; 如果前两位十进制数为零，则二进制输出的前六位为零。 因此，相同的编码可以灵活地用于将2个十进制数字编码为7个二进制位，以及1个十进制数到4个二进制位。 这使得它特别适用于基于两个（16位，32位，64位等）功率的标准计算机体系结构，因此不能被7或10直接整除。

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