公开(公告)号：US20060179098A1

公开(公告)日：2006-08-10

申请号：US11054234

申请日：2005-02-09

申请人： Michael Kelly ,  Wen Li ,  Eric Schwarz ,  Wai Wong

发明人： Michael Kelly ,  Wen Li ,  Eric Schwarz ,  Wai Wong

IPC分类号： G06F7/38

CPC分类号： G06F7/74 ,  G06F7/491 ,  G06F2207/4911

摘要： A method for leading zero detection. The method includes receiving DPD encoded data representing a three digit BCD number and determining directly from the DPD encoded data if the BCD number represented by the DPD encoded data contains at least one leading zero digit. A group one switch is set to zero if it was determined that the BCD number represented by the DPD encoded data contains at least one leading zero digit and set to one otherwise. The method also includes determining directly from the DPD encoded data if the BCD number represented by the DPD encoded data contains at least two leading zero digits. A group two switch is set to zero if it was determined that the BCD number represented by the DPD encoded data contains at least two leading zero digits and set to one otherwise. The method further includes determining directly from the DPD encoded data if the BCD number represented by the DPD encoded data contains three leading zero digits. A group three switch is set to zero if was determined that the BCD number represented by the DPD encoded data contains three leading zero digits and set to one otherwise.

摘要翻译： 一种引导零检测的方法。 如果由DPD编码数据表示的BCD数字包含至少一个前导零数字，则该方法包括接收表示三位BCD号码的DPD编码数据，并直接从DPD编码数据确定。 如果确定由DPD编码数据表示的BCD数字包含至少一个前导零数字并且另外设置为一个，则将一组开关设置为零。 如果由DPD编码数据表示的BCD数字包含至少两个前导零数字，则该方法还包括直接从DPD编码数据确定。 如果确定由DPD编码数据表示的BCD数字包含至少两个前导零数字并且另外设置为一个，则组二开关被设置为零。 如果由DPD编码数据表示的BCD数字包含三个前导零数字，则该方法还包括直接从DPD编码数据确定。 如果确定由DPD编码数据表示的BCD数字包含三个前导零数字并且另外设置为一个，则组三开关被设置为零。

公开(公告)号：US20060179090A1

公开(公告)日：2006-08-10

申请号：US11054232

申请日：2005-02-09

申请人： Steven Carlough ,  Bruce Fleischer ,  Wen Li ,  Eric Schwarz

发明人： Steven Carlough ,  Bruce Fleischer ,  Wen Li ,  Eric Schwarz

IPC分类号： G06F7/00

CPC分类号： H03M7/12

摘要： A method for converting from binary to decimal. The method includes receiving a binary number, the binary number including one or more sets of bits. An accumulated sum is set to zero. The accumulated sum is in a binary coded decimal (BCD) format. The following loop is repeated for each set of bits in the binary number in order from the set of bits containing the most significant bit of the binary number to the set of bits containing the least significant bit of the binary number: the accumulated sum is converted into a 5,1 code format resulting in an interim sum. The loop also includes repeating for each next bit in the set in order from the most significant bit to the least significant bit in the set: doubling the interim sum; and replacing the least significant bit of the interim sum with the next bit. The last step in the loop includes converting the interim sum into the BCD format and storing the results of the converting in the accumulated sum. Once all of the sets of bits in the binary number have been processed through the loop, the accumulated sum is output as the final result.

摘要翻译： 一种从二进制转换为十进制的方法。 该方法包括接收二进制数，该二进制数包括一个或多个位组。 累积和设为零。 累加和是二进制编码十进制（BCD）格式。 从包含二进制数的最高有效位的位的集合到包含二进制数的最低有效位的位的位的顺序从二进制数中的每组位重复以下循环：累积和被转换 成为5,1代码格式，产生临时总和。 循环还包括从组中的最高有效位到最低有效位的顺序对集合中的每个下一个位进行重复：使中间和加倍; 并用下一位代替中间和的最低有效位。 循环的最后一步包括将中间和转换为BCD格式，并将转换的结果存储在累加和中。 一旦通过循环处理了二进制数的所有位组，就将输出累加和作为最终结果。

公开(公告)号：US20060179102A1

公开(公告)日：2006-08-10

申请号：US11055221

申请日：2005-02-10

申请人： Steven Carlough ,  Paulomi Kadakia ,  Wen Li ,  Eric Schwarz

发明人： Steven Carlough ,  Paulomi Kadakia ,  Wen Li ,  Eric Schwarz

IPC分类号： G06F7/52

CPC分类号： G06F7/4917 ,  G06F2207/5352

摘要： A method for performing decimal division including receiving a scaled divisor and dividend and storing a subset of the multiples of the scaled divisor. An accumulated quotient is initialized to be equal to zero, a first current remainder is initialized to be equal to the scaled dividend, and a second current remainder is initialized to be equal to the scaled dividend minus the scaled divisor. The following loop is performed until a selected number of quotient digits are produced. An estimated next quotient digit is calculated based on the first digit of the first current remainder. A temp remainder is selected to be either the first current remainder or the second current remainder based on the estimated next quotient digit. A first next remainder is calculated by subtracting one of the stored multiples from the temp remainder, where the stored multiple is selected based on a first digit of the first current remainder. A second next remainder is calculated by subtracting an other one of the stored multiples from the temp remainder, where the other one of the stored multiples is selected based on the first current remainder. An actual quotient digits is calculated based on the estimated next quotient digit, the first current remainder and the first next remainder. The accumulated quotient is updated with the actual next quotient digit. Finally, the first current remainder is set to be equal to the first next remainder and the second current remainder is set to be equal to the second next remainder.

公开(公告)号：US20060179101A1

公开(公告)日：2006-08-10

申请号：US11054567

申请日：2005-02-09

申请人： Steven Carlough ,  Wen Li ,  Eric Schwarz

发明人： Steven Carlough ,  Wen Li ,  Eric Schwarz

IPC分类号： G06F7/52

CPC分类号： G06F7/496 ,  G06F2207/4911

摘要： A system for performing decimal multiplication including input registers for inputting a multiplier and a multiplicand. The multiplier includes one or more digits. The system also includes one or more two cycle adders and mechanism. The mechanism receives the multiplier and the multiplicand into the input registers. A running sum is reset to zero. The mechanism also performs for each of the digits in the multiplier in order from least significant digit to most significant digit: creating a partial product of the digit and the multiplicand; and adding the partial product to the running sum using the two cycle adders. When the loop is completed for each of the digits in the multiplier, the mechanism outputs the running sum as the result.

公开(公告)号：US20060179099A1

公开(公告)日：2006-08-10

申请号：US11055231

申请日：2005-02-10

申请人： Steven Carlough ,  Wen Li ,  Eric Schwarz

发明人： Steven Carlough ,  Wen Li ,  Eric Schwarz

IPC分类号： G06F7/38

CPC分类号： G06F7/4912 ,  G06F2207/4911

摘要： A method for performing a decimal floating point operation. A first operand including a first coefficient and a first exponent is received. The method also includes receiving a second operand that includes a second coefficient and a second exponent. An operation associated with the first operand and the second operand is received. The operation is an addition or a subtraction. Three concurrent calculations are performed on the first operand and the second operand. The first concurrent calculation includes applying the operation to the first operand and the second operand based on a first assumption that the first exponent is equal to the second exponent. The applying the operation based on the first assumption results in a first result and includes utilizing a two cycle adder. The second concurrent calculation includes applying the operation to the first operand and the second operand based on a second assumption that an absolute difference between the first exponent and the second exponent is less than or equal to a number of leading zeros in the coefficient of the operand with the larger exponent. The applying the operation based on the second assumption results in a second result and includes utilizing the two cycle adder. The third concurrent calculation includes applying the operation to the first operand and the second operand based on a third assumption that the absolute difference between the first exponent and the second exponent is greater than the number of leading zeros in the coefficient of the operand with the larger exponent. The applying the operation based on the third assumption results in a third result and includes utilizing the two cycle adder. A final result is selected from the first result, the second result and the third result.

公开(公告)号：US20060179103A1

公开(公告)日：2006-08-10

申请号：US11054687

申请日：2005-02-09

申请人： Steven Carlough ,  Wilhelm Haller ,  Wen Li ,  Eric Schwarz

发明人： Steven Carlough ,  Wilhelm Haller ,  Wen Li ,  Eric Schwarz

IPC分类号： G06F7/50

CPC分类号： G06F7/4912 ,  G06F7/483 ,  G06F7/507

摘要： A system for performing decimal floating point addition. The system includes input registers for inputting a first and second operand for an addition operation. The system also includes a plurality of adder blocks, each calculating a sum of one or more corresponding digits from the first operand and the second operand. Output from each of the adder blocks includes the sum of the corresponding digits and a carry out indicator for the corresponding digits. The calculating is performed during a first clock cycle. The system also includes an intermediate result register for storing the sums of the corresponding digits output from each of the plurality of adder blocks, the storing during the first clock cycle. The system further includes a carry chain for storing the carry out indicator output from each of the plurality of adder blocks, the storing occurring during the first clock cycle. The system further includes an incrementer for adding one to each of the sums stored in the intermediate result register, the incrementing occurring during a second clock cycle. In addition, a mechanism is provided for selecting between each of the sums and the sums incremented by one. The input to the mechanism includes the carry chain. The output includes the final sum of the first operand and the second operand. The selecting occurs during the second clock cycle.

公开(公告)号：US20060179091A1

公开(公告)日：2006-08-10

申请号：US11054233

申请日：2005-02-09

申请人： Steven Carlough ,  Bruce Fleischer ,  Wen Li ,  Eric Schwarz

发明人： Steven Carlough ,  Bruce Fleischer ,  Wen Li ,  Eric Schwarz

IPC分类号： G06F7/00

CPC分类号： H03M7/12

摘要： A method for converting from binary to decimal. The method includes receiving a binary coded decimal (BCD) number made up of one or more sets of three digits. A running sum and a running carry are set to zero. The following steps are performed for each set of three digits in the BCD number in order from the set of three digits containing the three most significant digits of the BCD number to the set of three digits containing the three least significant digits of the BCD number. The steps include: creating six partial products based on the set of three digits, the running sum and the running carry; combining the six partial products into two partial products; and storing the two partial products in the running sum and the running carry. After the loop has been performed for each set of three digits in the BCD number, the running sum and the running carry are combined into a final binary result.

摘要翻译： 一种从二进制转换为十进制的方法。 该方法包括接收由一个或多个三位数字组成的二进制编码十进制（BCD）号码。 运行总和和运行进位设置为零。 对于BCD号码中的每一组三位数字，按照从包含BCD号码三个最高有效数字的三位数字到包含BCD号码三个最低有效位数字的三位数组的顺序执行以下步骤。 步骤包括：根据三位数字，运行总和和运行进位创建六个部分产品; 将六部分产品合并成两部分产品; 并将两个部分乘积存储在运行和运行中。 在对BCD号码中的每组三位数进行了循环之后，运行总和和运行进位被组合成最终的二进制结果。

公开(公告)号：US20060184603A1

公开(公告)日：2006-08-17

申请号：US11056036

申请日：2005-02-11

申请人： Son Trong ,  Mark Erle ,  Bruce Fleischer ,  Juergen Haess ,  Michael Kelly ,  Klaus Kroener ,  Martin Schmookler ,  Eric Schwarz

发明人： Son Trong ,  Mark Erle ,  Bruce Fleischer ,  Juergen Haess ,  Michael Kelly ,  Klaus Kroener ,  Martin Schmookler ,  Eric Schwarz

IPC分类号： G06F7/52

CPC分类号： G06F7/53 ,  G06F7/74

摘要： The present invention relates to a method and circuit for performing multiply-operations in an arithmetic unit of a computer processor. In a multiplier thereof, zero detection of the resulting product bit string (22) is needed for a proper setting of condition code and overflow status information. Zero detection according to prior art decreases the calculation speed in the multiplier. In order to provide a method and respective electronic circuit, wherein the zero detection is earlier completed, it is proposed to use a leading zero anticipation (LZA) hardware—i.e., an LZA circuit (40), which exists usually anyway in floating point processor adders for calculating the number of leading zeros for operand normalization purposes—for performing a zero detection of the product by aid of the partial results (16, 17) emerging at the output of the Wallace tree of the multiplier. MSB-most and LSB-most margin bits (24, 26) of the partial (16, 17) results which cannot be processed by the LZA circuit (40), are read directly from the final product bit string (22).

摘要翻译： 本发明涉及一种用于在计算机处理器的运算单元中执行乘法运算的方法和电路。 在其乘数中，为了适当地设置条件代码和溢出状态信息，需要对所得到的产品位串（22）进行零检测。 根据现有技术的零检测降低了乘法器中的计算速度。 为了提供一种方法和各自的电子电路，其中零检测较早完成，提出使用前导零预期（LZA）硬件即LZA电路（40），其通常在浮点处理器 用于计算操作数归一化目的的前导零数量的加法器，用于通过在乘法器的华莱士树的输出处出现的部分结果（16,17）执行零检测。 从最终产品位串（22）直接读取不能由LZA电路（40）处理的部分（16,17）结果的MSB最大和LSB最大的边缘位（24,26）。

公开(公告)号：US08938605B2

公开(公告)日：2015-01-20

申请号：US12718685

申请日：2010-03-05

申请人： Fadi Busaba ,  Bruce Giamei ,  David Hutton ,  Eric Schwarz

发明人： Fadi Busaba ,  Bruce Giamei ,  David Hutton ,  Eric Schwarz

IPC分类号： G06F9/30 ,  G06F9/34

CPC分类号： G06F9/342 ,  G06F9/3017 ,  G06F9/30174 ,  G06F9/30181 ,  G06F9/30189

摘要： A method, information processing system, and computer program product manage instruction execution based on machine state. At least one instruction is received. The at least one instruction is decoded. A current machine state is determined in response to the decoding. The at least one instruction is organized into a set of unit of operations based on the current machine state that has been determined. The set of unit of operations is executed.

摘要翻译： 一种基于机器状态的方法，信息处理系统和计算机程序产品管理指令执行。 至少接收一条指令。 至少一条指令被解码。 响应于解码确定当前机器状态。 基于已经确定的当前机器状态将至少一个指令组织成一组操作单元。 执行一组操作单元。

公开(公告)号：US20110154298A1

公开(公告)日：2011-06-23

申请号：US12645687

申请日：2009-12-23

申请人： Gregory W. Alexander ,  Jane Bartik ,  Michael Billeci ,  David Hutton ,  Christian Jacobi ,  Jang-Soo Lee ,  Eric Schwarz ,  Chung-Lung Shum ,  Phil C. Yeh

发明人： Gregory W. Alexander ,  Jane Bartik ,  Michael Billeci ,  David Hutton ,  Christian Jacobi ,  Jang-Soo Lee ,  Eric Schwarz ,  Chung-Lung Shum ,  Phil C. Yeh

IPC分类号： G06F9/44

CPC分类号： G06F11/348 ,  G06F11/3409

摘要： A system and method for collecting instrumentation data in a processor with a pipelined instruction execution stages arranged in an out-of-order execution architecture. One instruction group in a Global Completion Table is marked as a tagged group. Instrumentation data is stored for processing stages processing instructions associated with the tagged group. Sample signal pulses trigger a determination of whether the tagged group is the next-to-complete instruction group. When the sample pulse occurs at a time when the tagged group is the next-to-complete group, the instrumentation data is written as an output. Instrumentation data present during sample pulses that occur when the tagged group is not the next-to-complete group is optionally discarded. Sample pulses are generated at a rate equal to the desired sample rate times the number of groups in the global completion table to better ensure occurrence of a next-to-complete tagged group.

摘要翻译： 一种用处理器收集仪器数据的系统和方法，其中流水线指令执行阶段以无序执行体系结构排列。 全局完成表中的一个指令组被标记为标记组。 存储用于与标记组相关联的处理阶段处理指令的仪表数据。 采样信号脉冲触发确定标记的组是否是下一个完成指令组。 当标记的组是下一个完成组时，当采样脉冲发生时，仪表数据被写为输出。 当标记的组不是下一个到完整的组时发生的采样脉冲期间存在的仪器数据被任选地丢弃。 以等于所需采样率的速率乘以采样脉冲乘以全局完成表中的组数，以更好地确保下一个到完整标记组的发生。