公开(公告)号：US11520500B2

公开(公告)日：2022-12-06

申请号：US17207436

申请日：2021-03-19

Applicant: Micron Technology, Inc.

Inventor： Luca Bert

IPC: G06F3/06

Abstract: A system and method for managing a reduction in capacity of a memory sub-system. An example method involving a memory sub-system: detecting a failure of a memory device of the set, wherein the memory device stores multiple bits per memory cell; sending a message to a host system indicating a reduced capacity of the set of memory devices; receiving from the host system a message to continue at the reduced capacity; and updating the set of memory devices based on the reduced capacity, wherein the updating comprises reducing a quantity of bits stored per memory cell of the memory device.

公开(公告)号：US20220334759A1

公开(公告)日：2022-10-20

申请号：US17855579

申请日：2022-06-30

Applicant: Micron Technology, Inc.

Inventor： Abdelhakim Alhussien ,  Ayberk Ozturk ,  Karl D. Schuh ,  Luca Bert

IPC: G06F3/06

Abstract: Data from a host system is received at a memory device, where the memory device includes a primary region to initially store the data received from the host system and one or more secondary regions to store data transferred from the primary region. A write operation is performed on one or more write units of the primary region with the data received from the host system, where a write unit of the primary region has lower density blocks than a write unit of the secondary region. Whether a subset of write units of the primary region corresponding to a pre-determined number of write units is written with at least a portion of the data received from the host system is determined. In response to determining that the subset of write units of the primary region is written, another write operation is performed on at least one write units of the secondary region with respective data of the subset of write units of the primary region.

公开(公告)号：US20220276887A1

公开(公告)日：2022-09-01

申请号：US17742299

申请日：2022-05-11

Applicant: Micron Technology, Inc.

Inventor： Luca Bert

IPC: G06F9/455 ,  G06F12/02 ,  G06F13/38 ,  G06F3/06

Abstract: A processing device, operatively coupled with a memory component, is configured to provide a plurality of virtual memory controllers and to provide a plurality of physical functions, wherein each of the plurality of physical functions corresponds to a different one of the plurality of virtual memory controllers. The processing device further presents the plurality of physical functions to a host computing system over a peripheral component interconnect express (PCIe) interface, wherein each of the plurality of physical functions corresponds to a different virtual machine running on the host computing system, and manages input/output (IO) operations received from the host computing systems and directed to the plurality of physical functions, as well as background operations performed on the memory component, in view of class of service parameters associated with the plurality of physical functions.

公开(公告)号：US11429544B2

公开(公告)日：2022-08-30

申请号：US17159487

申请日：2021-01-27

Applicant: Micron Technology, Inc.

Inventor： Joseph H. Steinmetz ,  Luca Bert ,  William Akin

IPC: G06F11/00 ,  G06F13/16 ,  G06F11/07 ,  G06F13/42

Abstract: A host command is received to configure a system to have a configuration designating an interface standard for exposing a storage element and a persistent memory region (PMR). The storage element is visible to a first protocol of the interface standard and the PMR is visible to a second protocol of the interface standard. The storage element is implemented on a first memory device of the system including a non-volatile memory device and the PMR is implemented on a second memory device of the system. The system is configured in accordance with the configuration.

公开(公告)号：US20220075551A1

公开(公告)日：2022-03-10

申请号：US16948275

申请日：2020-09-10

Applicant: Micron Technology, Inc.

Inventor： Abdelhakim Alhussien ,  Ayberk Ozturk ,  Karl D. Schuh ,  Luca Bert

IPC: G06F3/06

Abstract: Data from a host system is received at a memory device, where the memory device includes a primary region to initially store the data received from the host system and one or more secondary regions to store data transferred from the primary region. A write operation is performed on one or more write units of the primary region with the data received from the host system, where a write unit of the primary region has lower density blocks than a write unit of the secondary region. Whether a subset of write units of the primary region corresponding to a pre-determined number of write units is written with at least a portion of the data received from the host system is determined. In response to determining that the subset of write units of the primary region is written, another write operation is performed on at least one write units of the secondary region with respective data of the subset of write units of the primary region.

公开(公告)号：US20250077084A1

公开(公告)日：2025-03-06

申请号：US18776341

申请日：2024-07-18

Applicant: Micron Technology, Inc.

Inventor： Luca Bert

IPC: G06F3/06

Abstract: Various embodiments provide for processing write requests on a memory system based on queue identifiers and thread identification associated with the write requests. In particular, various embodiments can leverage queue identifiers and memory address information included in write requests to separate, associate those write request to threads (e.g., virtual thread) tracked by the memory system, and coalesce multiple write requests associated with a single thread into a single (larger) write to a sequence of blocks.

公开(公告)号：US20250053509A1

公开(公告)日：2025-02-13

申请号：US18775184

申请日：2024-07-17

Applicant: Micron Technology, Inc.

Inventor： Luca Bert

IPC: G06F12/02

Abstract: The disclosure configures a memory sub-system controller to perform Redundant Array of Independent Disks (RAID) stripe deletion based on physical region size. The controller stores a set of data across a plurality of memory components, a first of the plurality of components being configured to store data in a first set of regions, a second of the plurality of components being configured to store data in a second set of regions. The controller generates a plurality of error correction parity information stripes for multiple collections of the set of data and computes a quantity of the plurality of error correction parity information stripes to delete based on sizes of each region in the first and second sets of regions. The controller deletes one or more of the plurality of error correction parity information stripes based on the computed quantity.

公开(公告)号：US20250004655A1

公开(公告)日：2025-01-02

申请号：US18883900

申请日：2024-09-12

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Luca Bert

IPC: G06F3/06

Abstract: A set of host data items is received for storage at a memory sub-system. Each of the set of host data items is associated with a common data type. A zone group size metric associated with the common data type is identified among a set of zone group size metrics each associated with a distinct data type. The set of host data items are programmed to memory cells of a zone group having a zone group size indicated by the zone group size metric.

公开(公告)号：US20240353999A1

公开(公告)日：2024-10-24

申请号：US18759614

申请日：2024-06-28

Applicant: Micron Technology, Inc.

Inventor： Luca Bert

IPC: G06F3/06

CPC classification number: G06F3/0604 ,  G06F3/0619 ,  G06F3/0652 ,  G06F3/0673

Abstract: A victim management unit (MU) for performing a media management operation is identified. The victim MU stores valid data. A source cursor associated with the victim MU is identified from an ordered set of cursors. A target cursor following the source cursor in the ordered set of cursors referencing one or more available MUs is identified. In response to determining that the source cursor is a last cursor in the ordered set of cursors, the source cursor is utilized as the target cursor. The valid data is associated with the identified target cursor.

公开(公告)号：US20240248615A1

公开(公告)日：2024-07-25

申请号：US18624547

申请日：2024-04-02

Applicant: Micron Technology, Inc.

Inventor： Joseph Harold Steinmetz ,  Luca Bert

IPC: G06F3/06

CPC classification number: G06F3/0619 ,  G06F3/0659 ,  G06F3/067

Abstract: An apparatus with a solid state drive (SSD) having firmware to farm proof of space plots stored outside of the SSD. The SSD has a communication interface configured to receive at least read commands and write commands from an external host system. The SSD has memory cells formed on at least one integrated circuit die, and a processing device configured to control executions of the read commands to retrieve data from the memory cells and executions the write commands to store data into the memory cells. The firmware is executable in the SSD to receive and store configuration data specified via a user interface to indicate a location, outside of the SSD, storing a proof of space plot that can be used by the SSD to participate in proof of space activities in a cryptocurrency network.