公开(公告)号：US20080028129A1

公开(公告)日：2008-01-31

申请号：US10598307

申请日：2005-02-25

申请人： Masahiro Nakanishi ,  Tomoaki Izumi ,  Tetsushi Kasahara ,  Kazuaki Tamura ,  Kiminori Matsuno ,  Manabu Inoue

发明人： Masahiro Nakanishi ,  Tomoaki Izumi ,  Tetsushi Kasahara ,  Kazuaki Tamura ,  Kiminori Matsuno ,  Manabu Inoue

IPC分类号： G06F12/00

CPC分类号： G06F11/1441 ,  G06F11/1435

摘要： A writing completion flag table (105) for storing a writing completion flag corresponding to a predetermined storage unit such as a cluster or a physical block is stored in a non-volatile control memory (106). When completion of data writing into a predetermined storage unit is detected, a write completion flag is written in the corresponding address of the storage unit on the write completion flag table (105). Thus, it is possible to recognize that data has been written normally. Even when the flag indicating completion of writing into a page of the writing unit of the main storage memory cannot be written, it is possible to improve the writing reliability.

摘要翻译： 用于存储与诸如集群或物理块的预定存储单元相对应的写入完成标志的写入完成标志表（105）被存储在非易失性控制存储器（106）中。 当检测到写入预定存储单元的数据写入完成时，在写入完成标志表（105）上将写入完成标志写入存储单元的相应地址。 因此，可以认识到数据已被正常写入。 即使当指示写入主存储器的写入单元的页面的完成的标志不能被写入时，也可以提高写入可靠性。

公开(公告)号：US07793192B2

公开(公告)日：2010-09-07

申请号：US11568470

申请日：2005-04-25

申请人： Kazuaki Tamura ,  Tomoaki Izumi ,  Tetsushi Kasahara ,  Masahiro Nakanishi ,  Kiminori Matsuno ,  Manabu Inoue

发明人： Kazuaki Tamura ,  Tomoaki Izumi ,  Tetsushi Kasahara ,  Masahiro Nakanishi ,  Kiminori Matsuno ,  Manabu Inoue

IPC分类号： H03M13/03

CPC分类号： G11C16/22 ,  G06F11/1068 ,  G11C16/3418 ,  G11C2029/0409

摘要： A semiconductor memory device in which data is not written in a transfer destination under a state including an error when an error occurs at the time of reading data at the transfer destination. The semiconductor memory device (1) comprising a nonvolatile memory (2) having a data writing unit smaller than a physical block is provided with an error detecting/correcting circuit (23) in the non-volatile memory (2). When data stored in a specified block of the non-volatile memory (2) is transferred to a different physical block and written, the error detecting/correcting circuit (23) performs error detection and correction of data.

摘要翻译： 一种半导体存储器件，其中当在传送目的地读取数据时发生错误时，在包括错误的状态下，数据未被写入转移目的地。 包括具有比物理块小的数据写入单元的非易失性存储器（2）的半导体存储器件（1）在非易失性存储器（2）中设置有错误检测/校正电路（23）。 当存储在非易失性存储器（2）的指定块中的数据被传送到不同的物理块并写入时，错误检测/校正电路（23）执行数据的错误检测和校正。

公开(公告)号：US07610435B2

公开(公告)日：2009-10-27

申请号：US10598307

申请日：2005-02-25

申请人： Masahiro Nakanishi ,  Tomoaki Izumi ,  Tetsushi Kasahara ,  Kazuaki Tamura ,  Kiminori Matsuno ,  Manabu Inoue

发明人： Masahiro Nakanishi ,  Tomoaki Izumi ,  Tetsushi Kasahara ,  Kazuaki Tamura ,  Kiminori Matsuno ,  Manabu Inoue

IPC分类号： G06F12/10

CPC分类号： G06F11/1441 ,  G06F11/1435

摘要： A writing completion flag table that stores a writing completion flag corresponding to a predetermined storage, such as a cluster or a physical block, is stored in a non-volatile control memory. When completion of data writing into a predetermined storage is detected, a write completion flag is written in the corresponding address of the storage on the write completion flag table. Thus, it is possible to recognize that data has been written normally. Even when the flag indicating completion of writing into a page of the writing unit of the main storage memory cannot be written, it is possible to improve the writing reliability.

摘要翻译： 存储与诸如集群或物理块的预定存储相对应的写入完成标志的写入完成标志表存储在非易失性控制存储器中。 当检测到写入预定存储器的数据写入完成时，写入完成标志被写入写入完成标志表上的存储器的对应地址。 因此，可以认识到数据已被正常写入。 即使当指示写入主存储器的写入单元的页面的完成的标志不能被写入时，也可以提高写入可靠性。

公开(公告)号：US20070277076A1

公开(公告)日：2007-11-29

申请号：US11568470

申请日：2005-04-25

申请人： Kazuaki Tamura ,  Tomoaki Izumi ,  Tetsushi Kasahara ,  Masahiro Nakanishi ,  Kiminori Matsuno ,  Manabu Inoue

发明人： Kazuaki Tamura ,  Tomoaki Izumi ,  Tetsushi Kasahara ,  Masahiro Nakanishi ,  Kiminori Matsuno ,  Manabu Inoue

IPC分类号： G06F12/16 ,  G11C16/06 ,  G11C29/00

CPC分类号： G11C16/22 ,  G06F11/1068 ,  G11C16/3418 ,  G11C2029/0409

摘要： A semiconductor memory device in which data is not written in a transfer destination under a state including an error when an error occurs at the time of reading data at the transfer destination. The semiconductor memory device (1) comprising a nonvolatile memory (2) having a data writing unit smaller than a physical block is provided with an error detecting/correcting circuit (23) in the non-volatile memory (2). When data stored in a specified block of the non-volatile memory (2) is transferred to a different physical block and written, the error detecting/correcting circuit (23) performs error detection and correction of data.

摘要翻译： 一种半导体存储器件，其中当在传送目的地读取数据时发生错误时，在包括错误的状态下，数据未被写入转移目的地。 包括具有比物理块小的数据写入单元的非易失性存储器（2）的半导体存储器件（1）在非易失性存储器（2）中设置有错误检测/校正电路（23）。 当存储在非易失性存储器（2）的指定块中的数据被传送到不同的物理块并写入时，错误检测/校正电路（23）执行数据的错误检测和校正。

公开(公告)号：US07849382B2

公开(公告)日：2010-12-07

申请号：US11568564

申请日：2005-05-12

申请人： Tetsushi Kasahara ,  Tomoaki Izumi ,  Masahiro Nakanishi ,  Kazuaki Tamura ,  Kiminori Matsuno ,  Yoshihisa Inagaki ,  Manabu Inoue

发明人： Tetsushi Kasahara ,  Tomoaki Izumi ,  Masahiro Nakanishi ,  Kazuaki Tamura ,  Kiminori Matsuno ,  Yoshihisa Inagaki ,  Manabu Inoue

IPC分类号： G11C29/00

CPC分类号： G11C16/10 ,  G06F11/1068

摘要： An address at which a writing error occurs is held, and after a completion of a series of writings, the data of the held address is read. Then, a faulty-block processing is performed only for the addresses, for which it is determined that retry of writing is required, thereby preventing an increase of faulty-blocks. This can suppress the problem that when a writing is performed in a particular flash memory, a writing error frequently occurs and a large number of faulty blocks occur.

摘要翻译： 发生写入错误的地址被保持，并且在一系列写入完成之后，读取保持的地址的数据。 然后，仅对于确定需要重写写入的地址执行错误块处理，从而防止错误块的增加。 这可以抑制在特定闪速存储器中执行写入时经常发生写入错误并发生大量错误块的问题。

公开(公告)号：US20080049504A1

公开(公告)日：2008-02-28

申请号：US11568564

申请日：2005-05-12

申请人： Tetsushi Kasahara ,  Tomoaki Izumi ,  Masahiro Nakanishi ,  Kazuaki Tamura ,  Kiminori Matsuno ,  Yoshihisa Inagaki ,  Manabu Inoue

发明人： Tetsushi Kasahara ,  Tomoaki Izumi ,  Masahiro Nakanishi ,  Kazuaki Tamura ,  Kiminori Matsuno ,  Yoshihisa Inagaki ,  Manabu Inoue

IPC分类号： G11C16/06

CPC分类号： G11C16/10 ,  G06F11/1068

摘要： An address at which a writing error occurs is held, and after a completion of a series of writings, the data of the held address is read. Then, a faulty-block processing is performed only for the addresses, for which it is determined that retry of writing is required, thereby preventing an increase of faulty-blocks. This can suppress the problem that when a writing is performed in a particular flash memory, a writing error frequently occurs and a large number of faulty blocks occur.

摘要翻译： 发生写入错误的地址被保持，并且在一系列写入完成之后，读取保持的地址的数据。 然后，仅对于确定需要重写写入的地址执行错误块处理，从而防止错误块的增加。 这可以抑制在特定闪速存储器中执行写入时经常发生写入错误并发生大量错误块的问题。

公开(公告)号：US20080109627A1

公开(公告)日：2008-05-08

申请号：US11718965

申请日：2005-11-08

申请人： Masayuki Toyama ,  Tomoaki Izumi ,  Kazuaki Tamura ,  Kiminori Matsuno ,  Manabu Inoue ,  Masahiro Nakanishi

发明人： Masayuki Toyama ,  Tomoaki Izumi ,  Kazuaki Tamura ,  Kiminori Matsuno ,  Manabu Inoue ,  Masahiro Nakanishi

IPC分类号： G06F12/00

CPC分类号： G06F13/1647 ,  G06F12/0607

摘要： The present invention provides a nonvolatile memory device that can be used in combination with a plurality of types of memory controllers that are different in number of banks to be simultaneously accessed, the nonvolatile memory device being also capable of achieving high-speed access.The nonvolatile memory device of the present invention includes: a memory area divided into a plurality of banks from/to which data can be read/written independently; and data registers for storing data that has been read from the memory area or that is to be written to the memory area, the data registers being at least equal in number to the banks, and connections between the banks and the data registers are changed in accordance with the number of banks that are to be simultaneously accessed.

摘要翻译： 本发明提供一种非易失性存储器件，其可以与要同时存取的存储体数不同的多种存储器控制器组合使用，非易失性存储器件也能够实现高速存取。 本发明的非易失性存储装置包括：分割成可独立读/写数据的多个存储体的存储区域; 以及数据寄存器，用于存储已经从存储器区域读取或要写入存储区域的数据，数据寄存器的数量至少等于存储区，并且存储体和数据寄存器之间的连接被改变为 按照同时访问的银行数量。

公开(公告)号：US20090055618A1

公开(公告)日：2009-02-26

申请号：US11814202

申请日：2006-07-21

申请人： Masahiro Nakanishi ,  Tetsushi Kasahara ,  Tomoaki Izumi ,  Kiminori Matsuno ,  Daisuke Kunimune ,  Kazuaki Tamura ,  Yoshiyuki Konishi

发明人： Masahiro Nakanishi ,  Tetsushi Kasahara ,  Tomoaki Izumi ,  Kiminori Matsuno ,  Daisuke Kunimune ,  Kazuaki Tamura ,  Yoshiyuki Konishi

IPC分类号： G06F12/02 ,  G06F12/00 ,  G06F12/06

CPC分类号： G06F12/0246 ,  G06F2212/1036 ,  G06F2212/7211

摘要： For address management of a nonvolatile memory, the whole logical address space is divided into logical address ranges (0 to 15), and the physical address space is divided into physical areas (segments (0 to 15)). The logical address ranges are respectively associated with the physical areas (segments) to manage the addresses. The sizes of the logical address ranges are equalized. The size of the physical area (segment (0)) corresponding to the logical address range (0) in which data of high rewrite frequency such as an FAT is expected to be stored is larger than those of the other physical areas, and the logical address ranges and the physical areas are allocated. Alternatively, the sizes of the physical areas are equalized, and the size of the logical address range (0) is set as a smaller one than those of the other logical address ranges. With this, the actual rewrite frequencies of the physical areas (segments) are equal to one another, and consequently the life of the nonvolatile memory can be prolonged.

摘要翻译： 对于非易失性存储器的地址管理，整个逻辑地址空间被划分为逻辑地址范围（0至15），物理地址空间被划分为物理区域（段（0至15））。 逻辑地址范围分别与物理区域（段）相关联以管理地址。 逻辑地址范围的大小相等。 对应于期望存储诸如FAT的高重写频率的数据的逻辑地址范围（0）的物理区域（段（0））的大小大于其他物理区域的大小，并且逻辑 地址范围和物理区域被分配。 或者，物理区域的大小相等，并且逻辑地址范围（0）的大小被设置为比其他逻辑地址范围的大小小。 由此，物理区域（段）的实际重写频率彼此相等，因此可以延长非易失性存储器的寿命。

公开(公告)号：US20060190670A1

公开(公告)日：2006-08-24

申请号：US10553974

申请日：2004-10-13

申请人： Masahiro Nakanishi ,  Tomoaki Izumi ,  Tetsushi Kasahara ,  Kazuaki Tamura ,  Kiminori Matsuno

发明人： Masahiro Nakanishi ,  Tomoaki Izumi ,  Tetsushi Kasahara ,  Kazuaki Tamura ,  Kiminori Matsuno

IPC分类号： G06F12/06 ,  G06F12/00

CPC分类号： G06F12/06 ,  G06F2212/2022

摘要： A controller 102 and four flash memories F0 to F3 are connected by twos to two memory buses, and each flash memory is divided into two regions of substantially the same size to form a first half and a last half regions. In a four-memory configuration, a consecutive logical address specified by a host apparatus is divided into a predetermined size, and a write operation is performed in a format that repeatedly circulates through F0, F1, F2, F3 in this order. In a two-memory configuration, the write operation is performed in a format that repeatedly circulates through F00, F10, F01, F11. Thus, a controller processing is made common regardless of the number of flash memories connected to the controller.

摘要翻译： 控制器102和四个闪速存储器F 0至F 3通过两个连接到两个存储器总线，并且每个闪速存储器被划分为大致相同大小的两个区域，以形成前半部分和后半个区域。 在四存储器配置中，由主机设备指定的连续逻辑地址被划分为预定大小，并以按顺序重复循环的格式执行写入操作。 。 在双存储器配置中，写入操作以通过F 00，F 10，F 01，F 11重复循环的格式执行。因此，无论连接到控制器的闪存数量如何，控制器处理都是常见的 。

公开(公告)号：US08051268B2

公开(公告)日：2011-11-01

申请号：US11814202

申请日：2006-07-21

申请人： Masahiro Nakanishi ,  Tetsushi Kasahara ,  Tomoaki Izumi ,  Kiminori Matsuno ,  Daisuke Kunimune ,  Kazuaki Tamura ,  Yoshiyuki Konishi

发明人： Masahiro Nakanishi ,  Tetsushi Kasahara ,  Tomoaki Izumi ,  Kiminori Matsuno ,  Daisuke Kunimune ,  Kazuaki Tamura ,  Yoshiyuki Konishi

IPC分类号： G06F12/00

CPC分类号： G06F12/0246 ,  G06F2212/1036 ,  G06F2212/7211

摘要： For address management of a nonvolatile memory, the whole logical address space is divided into logical address ranges (0 to 15), and the physical address space is divided into physical areas (segments (0 to 15)). The logical address ranges are respectively associated with the physical areas (segments) to manage the addresses. The sizes of the logical address ranges are equalized. The size of the physical area (segment (0)) corresponding to the logical address range (0) in which data of high rewrite frequency such as an FAT is expected to be stored is larger than those of the other physical areas, and the logical address ranges and the physical areas are allocated. Alternatively, the sizes of the physical areas are equalized, and the size of the logical address range (0) is set as a smaller one than those of the other logical address ranges. With this, the actual rewrite frequencies of the physical areas (segments) are equal to one another, and consequently the life of the nonvolatile memory can be prolonged.

摘要翻译： 对于非易失性存储器的地址管理，整个逻辑地址空间被划分为逻辑地址范围（0至15），物理地址空间被划分为物理区域（段（0至15））。 逻辑地址范围分别与物理区域（段）相关联以管理地址。 逻辑地址范围的大小相等。 对应于期望存储诸如FAT的高重写频率的数据的逻辑地址范围（0）的物理区域（段（0））的大小大于其他物理区域的大小，并且逻辑 地址范围和物理区域被分配。 或者，物理区域的大小相等，并且逻辑地址范围（0）的大小被设置为比其他逻辑地址范围的大小小。 由此，物理区域（段）的实际重写频率彼此相等，因此可以延长非易失性存储器的寿命。