公开(公告)号：US5939909A

公开(公告)日：1999-08-17

申请号：US52187

申请日：1998-03-31

Applicant: Michael J. Callahan, Jr.

Inventor： Michael J. Callahan, Jr.

IPC: H03K4/00 ,  H03K4/94 ,  H03K17/16 ,  H03B1/00

CPC classification number: H03K17/166 ,  H03K17/163 ,  H03K4/00 ,  H03K4/94

Abstract: A driver circuit for a power device of a power driving stage is capable of providing slew rate control. The driver circuit includes the following elements: a charging source of current, a discharging source of current, a first switch, a second switch, a conductive device, a capacitive element, an amplifier, and the power device. Both the first and second switches receive a control signal. The elements of the driver circuit are configured such that the conductive device will conduct only when the following two conditions are met: the control signal is a certain logic level and the voltage generated by the amplifier is larger than a reference voltage. When the control signal transitions from a first to a second logic state, a charging current is delivered to the capacitive element, an output voltage of the driver circuit increased to the reference voltage, and a voltage on a control terminal of the power device also increases to a charge pump voltage level. When the control signal transitions from the second to the first logic state, the conductive device conducts as long as the output voltage generated by the power device is larger than the reference voltage and the discharging source of current operates to quickly discharge the capacitive element so that the voltage at the node at the input terminal of the amplifier is quickly reduced until it approximates the reference voltage.

Abstract translation: 用于动力驱动级的动力装置的驱动电路能够提供压摆率控制。 驱动器电路包括以下元件：电流充电源，电流放电源，第一开关，第二开关，导电器件，电容元件，放大器和功率器件。 第一和第二开关都接收控制信号。 驱动器电路的元件被配置为仅当满足以下两个条件时导通器件才会导通：控制信号是一定的逻辑电平，放大器产生的电压大于参考电压。 当控制信号从第一逻辑状态转变到第二逻辑状态时，将充电电流传送到电容元件，驱动电路的输出电压增加到参考电压，并且功率器件的控制端上的电压也增加 到电荷泵电压电平。 当控制信号从第二逻辑状态转变到第一逻辑状态时，只要由功率器件产生的输出电压大于参考电压并且电流放电源工作以使电容元件快速放电，导电器件就会导通，使得 放大器输入端节点处的电压迅速降低，直到其接近参考电压。

公开(公告)号：US5703617A

公开(公告)日：1997-12-30

申请号：US240026

申请日：1994-05-09

Applicant: Michael J. Callahan, Jr. ,  Christopher A. Ludden

Inventor： Michael J. Callahan, Jr. ,  Christopher A. Ludden

IPC: G02F1/133 ,  G09G3/20 ,  G09G3/36

CPC classification number: G09G3/2011 ,  G09G3/3688 ,  G09G3/3696 ,  G09G2310/027 ,  G09G2310/0281 ,  G09G2310/0289

Abstract: The present invention relates to a signal driver circuit for driving a liquid crystal display panel. The signal driver circuit provides level shifting within the circuit to lower the power consumption of a liquid crystal display module while still providing a wide analog voltage range to the liquid crystal display elements. The decoding circuits utilize a strand of abutting decode input transistors which are connected in series. Further to reduce the physical size of the decoding circuits, multiple decode circuits may share circuitry that decodes the most significant bits of a data word. A cell layout is utilized such that the most significant bits data are bused into the cell through metal lines and the least significant bits are bused in polysilicon that also operates as the gate of the decode input transistors. Moreover, the decode cell input transistors may all be of the same conductivity type.

Abstract translation: 本发明涉及用于驱动液晶显示面板的信号驱动电路。 信号驱动器电路在电路内提供电平移位以降低液晶显示模块的功耗，同时仍向液晶显示元件提供宽的模拟电压范围。 解码电路利用串联连接的解码输入晶体管。 为了减少解码电路的物理尺寸，多个解码电路可以共享解码数据字的最高有效位的电路。 利用单元格布局，使得最高有效位数据通过金属线被插入到单元中，并且最低有效位被叠加在也用作解码输入晶体管的栅极的多晶硅中。 此外，解码单元输入晶体管可以都是相同的导电类型。

公开(公告)号：US4943807A

公开(公告)日：1990-07-24

申请号：US180889

申请日：1988-04-13

Applicant: Adrian B. Early ,  Larry L. Harris ,  Michael J. Callahan, Jr.

Inventor： Adrian B. Early ,  Larry L. Harris ,  Michael J. Callahan, Jr.

IPC: H03M3/02

CPC classification number: H03M3/38 ,  H03M3/458

Abstract: A self-calibrated analog-to-digital converter with a corrected output includes an analog modulator (18) for receiving an analog input voltage and outputting a pulse train having a value proportional to the analog input voltage. The pulse train is filtered by a digital filter (20) which has the output thereof input to a calibration module (24). The calibration module (24) is controlled by a calibration control circuit (28) and is operable to correct the output to account for offset and gain errors. Prestored calibration parameters in a register (30) are utilized for this compensation. In a self-calibration mode, the control circuit (28) is operable to control a calibration multiplexer (12) to select a zero-scale input voltage on a terminal (16) and a full-scale reference voltage on a terminal (14) for input to the modulator (18). The multiplexer (12) is controlled to selcet the zero-scale reference to calculate an offset value for storage in the register (30) and then subsequently select the full-scale reference to calculate a scale factor for storage in the register (30 ). The self-calibration mode utilizes a settling counter (36) to insure that the output of the filter (20) has settled prior to making any calculations.

Abstract translation: 具有校正输出的自校准模数转换器包括用于接收模拟输入电压并输出具有与模拟输入电压成比例的值的脉冲串的模拟调制器（18）。 脉冲串被数字滤波器（20）滤波，数字滤波器（20）的输出被输入到校准模块（24）。 校准模块（24）由校准控制电路（28）控制，并且可操作以校正输出以考虑偏移和增益误差。 寄存器（30）中的预先存储的校准参数用于此补偿。 在自校准模式中，控制电路（28）可操作以控制校准多路复用器（12），以选择端子（16）上的零电平输入电压和终端（14）上的满量程参考电压， 用于输入到调制器（18）。 多路复用器（12）被控制以选择零标度参考以计算用于存储在寄存器（30）中的偏移值，然后随后选择满量程参考以计算用于存储在寄存器（30）中的比例因子。 自校准模式利用沉降计数器（36）来确保过滤器（20）的输出在进行任何计算之前已经结算。