公开(公告)号：US11714576B2

公开(公告)日：2023-08-01

申请号：US17505046

申请日：2021-10-19

Applicant: Micron Technology, Inc.

Inventor： Scott E. Schaefer ,  Melissa I. Uribe

IPC: G06F13/16 ,  G06F3/06

CPC classification number: G06F3/0659 ,  G06F3/0614 ,  G06F3/0679 ,  G06F13/1668 ,  G06F2213/16

Abstract: Methods, systems, and devices for memory bus drive defect detection and related operations are described. A controller coupled with a memory array may receive a command for data. The memory array may include one or more pins for communicating data to and from the memory array, in response to the command. The controller may transmit to the memory array, over a bus that is coupled with the controller and the pins, the command. The controller may detect, based at least in part on a resistor coupled with the bus and a power supply of the memory array, that the bus is operating in a first state after transmitting the command. The first state may comprise a voltage that is relatively higher than a voltage of the second state. The controller may determine a defect associated with the bus or the pin based on detecting the bus in the first state.

公开(公告)号：US20230053384A1

公开(公告)日：2023-02-23

申请号：US17880220

申请日：2022-08-03

Applicant: Micron Technology, Inc.

Inventor： Melissa I. Uribe

IPC: G06F11/10

Abstract: Methods, systems, and devices for memory operations are described. A pin associated with communicating error correction information may be biased, via a first circuit, to a first voltage level by a first voltage source that is coupled with the pin when the pin is in an idle state. Also, a set of data pins may be biased, via a second circuit, to a second voltage level by a second voltage source when the set of data pins is in the idle state. When a memory device misses a command transmitted from a host device, the voltage levels of the pin and set of data pins may remain at the respective voltage levels throughout a period during which the host device executes an operation associated with the missed command, indicating to the host device that data communicated by a corresponding data signal is invalid.