公开(公告)号：US20190220346A1

公开(公告)日：2019-07-18

申请号：US15871594

申请日：2018-01-15

申请人： Microchip Technology Incorporated

发明人： Alain Vergnes ,  Eric Matulik ,  Marc Maunier

IPC分类号： G06F11/07 ,  G06F13/16 ,  G06F3/06 ,  G06F11/08

CPC分类号： G06F11/0796 ,  G06F3/061 ,  G06F3/0614 ,  G06F3/0629 ,  G06F11/08 ,  G06F13/1689 ,  G11C29/022 ,  G11C29/08 ,  G11C29/10 ,  G11C29/12 ,  G11C29/1201 ,  G11C29/34 ,  G11C29/36 ,  G11C29/38 ,  G11C29/52 ,  G11C2029/0409 ,  G11C2029/3602

摘要： A memory controller includes a generator circuit configured to generate a predetermined pattern of data, an address input, and a memory interface circuit. The memory interface circuit is configured to write the predetermined pattern of data to a memory at an address identified in the address input. The memory interface circuit is further configured to read a stored pattern of data from the memory at the address. The memory controller further includes an integrity checker circuit configured to compare the predetermined pattern of data and the stored pattern of data and identify an error of the memory based upon the comparison.

公开(公告)号：US20190079882A1

公开(公告)日：2019-03-14

申请号：US15964993

申请日：2018-04-27

申请人： Samsung Electronics Co., Ltd.

发明人： YoungWook KIM ,  Hyung-jin Kim ,  Soong-Man Shin ,  Keun-Hwan Lee

IPC分类号： G06F13/16 ,  G11C7/10 ,  G11C7/22 ,  G06F3/06

CPC分类号： G06F13/1689 ,  G06F3/0614 ,  G06F3/0658 ,  G06F3/0673 ,  G11C7/1009 ,  G11C7/1093 ,  G11C7/22 ,  G11C16/06 ,  G11C16/32 ,  G11C29/52 ,  G11C2207/2254

摘要： An operation method performed at a nonvolatile memory device may include receiving a program command and an address from an external device through a data signal (DQ), receiving a specific pattern from the external device through the data signal and a data strobe signal (DQS) synchronized with the data signal in a pattern period, receiving user data from the external device through the data signal and the data strobe signal in a data period, and selectively performing a program operation on the user data or a recovery operation based on a determination of whether the specific pattern matches with a particular pattern. A rising edge or a falling edge of the data strobe signal may be aligned with a left edge or a right edge of a window of the data signal in the pattern period.

公开(公告)号：US20190079694A1

公开(公告)日：2019-03-14

申请号：US15913949

申请日：2018-03-07

申请人： Toshiba Memory Corporation

发明人： Takahiro YAMAURA ,  Tomonori MAEGAWA ,  Masataka GOTO

IPC分类号： G06F3/06 ,  G06F12/02

CPC分类号： G06F3/0652 ,  G06F3/0614 ,  G06F3/0622 ,  G06F3/067 ,  G06F3/0679 ,  G06F12/0246 ,  G06F12/14 ,  G06F2212/7205

摘要： According to an embodiment, a storage device includes an acquisition unit, a first generation unit, and an erase unit. The acquisition unit is configured to acquire erase permission notification which is generated based on specific data and first authentication information to authenticate the specific data, and includes a first erase code to erase the specific data and physical area information indicating a physical area of the specific data. The first generation unit is configured to generate a second erase code using the specific data stored in the physical area indicated by the physical area information and the first authentication information. The erase unit is configured to erase data stored in the physical area indicated by the physical area information when the first erase code corresponds to the second erase code.

公开(公告)号：US20190074962A1

公开(公告)日：2019-03-07

申请号：US16108747

申请日：2018-08-22

申请人： Accenture Global Solutions Limited ,  GSC Secrypt, LLC

发明人： Giuseppe Ateniese ,  Michael T. Chiaramonte ,  David Treat

IPC分类号： H04L9/08 ,  H04L9/06 ,  G06F17/30 ,  G06F21/64 ,  H04L29/06

CPC分类号： G06F3/0622 ,  G06F3/0614 ,  G06F3/0629 ,  G06F3/0659 ,  G06F3/067 ,  G06F16/1805 ,  G06F16/182 ,  G06F21/645 ,  H04L9/0643 ,  H04L9/0816 ,  H04L9/085 ,  H04L9/3236 ,  H04L63/06 ,  H04L63/061 ,  H04L2209/38

摘要： A system includes circuitry for rewriting blockchains in a non-tamper-evident or tamper-evident operation by a trusted party during a rewrite-permissive phase. During a rewrite-embargoed phase, at least one trusted party with rewrite access during the rewrite-permissive phase may have rewrite access revoked. In some implementations, rewrite access may be implemented by controlling access to a key secret for the blockchain. In some cases, access to the key secret may be changed by deleting the key secret or by changing access permissions for a particular device.

公开(公告)号：US20190026022A1

公开(公告)日：2019-01-24

申请号：US15655294

申请日：2017-07-20

申请人： DELL PRODUCTS, LP

发明人： Chandrashekar Nelogal ,  Yogesh P. Kulkarni ,  Sanjeev Dambal ,  Sundar Dasar

IPC分类号： G06F3/06

CPC分类号： G06F3/061 ,  G06F3/0604 ,  G06F3/0614 ,  G06F3/0631 ,  G06F3/0658 ,  G06F3/0683

摘要： An information handling system includes storage drives, a first storage controller configured to map to a first subset of the storage drives, a second storage controller configured to map to a second subset of the storage drives different from the first subset, and a BMC. The BMC directs the storage controllers to detect storage traffic to the first and second subsets of storage drives, compares the storage traffic from the storage controllers, and remaps the first storage controller to map storage transactions on a third subset of the storage drives different from the first subset when the comparison indicates that the first storage traffic is greater than the second storage traffic.

公开(公告)号：US20190012097A1

公开(公告)日：2019-01-10

申请号：US15936017

申请日：2018-03-26

申请人： Silicon Motion, Inc.

发明人： Ching-Ke Chen ,  Chin-Fen Tung

IPC分类号： G06F3/06 ,  G11C16/22

CPC分类号： G06F3/0614 ,  G06F3/0653 ,  G06F3/0679 ,  G11C8/12 ,  G11C16/22 ,  G11C29/52 ,  G11C2029/4402

摘要： A non-volatile memory operated through multiple channels. The non-volatile memory includes a plurality of chip-enable-signal controlled areas, each containing a plurality of dies. Simultaneous operations on the different dies of at least one target chip-enable-signal controlled space corresponding to a target channel are allowed. The control unit scans the non-volatile memory to check the health status of the dies of the target chip-enable-signal controlled space to assign a plurality of logical enable signals of the target channel to correspond to the dies of the target chip-enable-signal controlled space.

公开(公告)号：US20180341417A1

公开(公告)日：2018-11-29

申请号：US16032288

申请日：2018-07-11

申请人： International Business Machines Corporation

发明人： Ilya Volvovski ,  Bruno H. Cabral ,  Manish Motwani ,  Thomas D. Cocagne ,  Timothy W. Markison ,  Gary W. Grube ,  Wesley B. Leggette ,  Jason K. Resch ,  Michael Colin Storm ,  Greg R. Dhuse ,  Yogesh R. Vedpathak ,  Ravi V. Khadiwala

IPC分类号： G06F3/06

CPC分类号： G06F3/0629 ,  G06F3/0614 ,  G06F3/067 ,  G06F11/1076

摘要： A method for execution by a processing system of a dispersed storage and task (DST) processing unit comprises: receiving one or more encoded data slices for storage; storing the one or more encoded data slices in one or more memories of a set of memories; determining a level redundancy for the one or more encoded data slices; generating redundancy information for the one or more encoded data slices in accordance with the level redundancy; storing the redundancy information in another one or more memories of the set of memories; determining to update the level of redundancy; determining an updated level of redundancy based on one or more of a storage utilization level and a storage reliability level; updating the redundancy information based on the updated level of redundancy and updating storage of the redundancy information based on the updated redundancy information.

公开(公告)号：US20180293022A1

公开(公告)日：2018-10-11

申请号：US15813543

申请日：2017-11-15

申请人： SK hynix Inc.

发明人： Byeong-Gyu PARK

IPC分类号： G06F3/06 ,  G06F12/0871 ,  G06F13/16

CPC分类号： G06F3/0656 ,  G06F3/0614 ,  G06F3/0659 ,  G06F3/0679 ,  G06F12/0871 ,  G06F13/161 ,  G06F13/1673 ,  G06F2003/0691 ,  G11C7/10

摘要： A controller includes: a first buffer suitable for buffering data read from a memory device; a second buffer suitable for buffering data to be written into the memory device; a processor suitable for, in response to a read command, controlling the memory device to read data therefrom and the first buffer to buffer the read data; and a buffer management unit suitable for, in response to the read command, providing the buffered data of the first buffer when the second buffer does not currently buffer data to be read.

公开(公告)号：US10084770B2

公开(公告)日：2018-09-25

申请号：US13289200

申请日：2011-11-04

申请人： Manish Motwani ,  Andrew Baptist

发明人： Manish Motwani ,  Andrew Baptist

IPC分类号： G06F12/06 ,  H04L29/06 ,  G06F3/06 ,  G06F11/10

CPC分类号： H04L63/0823 ,  G06F3/0605 ,  G06F3/0614 ,  G06F3/0643 ,  G06F3/0647 ,  G06F3/067 ,  G06F11/1076 ,  G06F12/06 ,  G06F2211/1057

摘要： A method begins by a processing module storing a plurality of encoded data slices in a plurality of memory devices of a dispersed storage (DS) unit of a dispersed storage network (DSN) memory using a quantity load balancing function to substantially balance a quantity of encoded data slices stored within each of the plurality of memory devices, wherein data size of at least some of the plurality of encoded data slices is different. The method continues with the processing module determining whether an available memory imbalance exists between a first memory device of the plurality of memory devices and a second memory device of the plurality of memory devices. The method continues with the processing module migrating one or more encoded data slices between the first and second memory devices to reduce the available memory imbalance when the available memory imbalance exists.

公开(公告)号：US10078455B2

公开(公告)日：2018-09-18

申请号：US15002216

申请日：2016-01-20

申请人： Microsoft Technology Licensing, LLC

发明人： Iyswarya Narayanan ,  Di Wang ,  Myeongjae Jeon ,  Bikash Sharma ,  Laura Marie Caulfield ,  Sriram Govindan ,  Benjamin Franklin Cutler ,  Christopher W. Hoder ,  Jaya Naga Satish Bobba ,  Jie Liu ,  Badriddine Khessib

IPC分类号： G06F3/06

CPC分类号： G06F3/0614 ,  G06F3/0605 ,  G06F3/0616 ,  G06F3/0631 ,  G06F3/067 ,  G06F3/0679 ,  G06F3/0683

摘要： Aspects extend to methods, systems, and computer program products for predicting solid state drive reliability. Aspects of the invention can be used to predict and/or to configure a data center to minimize one or more of: SSD capacity degradation (how much storage an SSD has left), SSD performance degradation (reduced read/write latency/throughput), and SSD failure. Models and data center considerations can be based on device level SSD related operations, such as, for example, read, write, erase. Operations decisions can be made for a data center based on SSD specific features, such as, for example, remaining capacity, write amplification factor, etc. Dependence and/or causality of various different data center factors can be leveraged. The impact of the various data center factors on different SSD failure modes and capacity/performance degradation can be quantified to drive SSD design, SSD provisioning, and SSD operations.