公开(公告)号：US10152262B2

公开(公告)日：2018-12-11

申请号：US15145628

申请日：2016-05-03

Applicant: Micron Technology, Inc.

Inventor： Shekoufeh Qawami ,  Rajesh Sundaram

IPC: G06F12/00 ,  G06F13/00 ,  G06F13/28 ,  G06F3/06

Abstract: Methods, systems, and devices for operating a memory array are described. A memory controller may be configured to provide enhanced bandwidth on a command/address (C/A) bus, which may have a relatively low pin count, through use of a next partition command that may repeat an array command from a current partition at a different partition indicated by the next partition command. Such a next partition command may use fewer clock cycles than a command that includes a complete instruction and memory location information.

公开(公告)号：US20170322749A1

公开(公告)日：2017-11-09

申请号：US15145628

申请日：2016-05-03

Applicant: Micron Technology, Inc.

Inventor： Shekoufeh Qawami ,  Rajesh Sundaram

IPC: G06F3/06

CPC classification number: G06F3/0644 ,  G06F3/061 ,  G06F3/0655 ,  G06F3/0679 ,  G06F12/00

Abstract: Methods, systems, and devices for operating a memory array are described. A memory controller may be configured to provide enhanced bandwidth on a command/address (C/A) bus, which may have a relatively low pin count, through use of a next partition command that may repeat an array command from a current partition at a different partition indicated by the next partition command. Such a next partition command may use fewer clock cycles than a command that includes a complete instruction and memory location information.