公开(公告)号：US20240361950A1

公开(公告)日：2024-10-31

申请号：US18660070

申请日：2024-05-09

Applicant: Micron Technology, Inc.

Inventor： Aaron P. Boehm ,  Steffen Buch ,  Lance W. Dover

IPC: G06F3/06

CPC classification number: G06F3/0655 ,  G06F3/0623 ,  G06F3/0679

Abstract: Methods, systems, and devices for host verification for a memory device are described. A memory device may receive a first value from a host device that is associated with an identification of the host device after an event. The memory device may transmit a second value to the host device that is based on the first value and comprises a random set of bits. The memory device may receive from the host device data or a command that comprises an encrypted third value that is based at least in part on the second value and a secret shared between the host device and the memory device. The memory device may also enable a functionality of the memory device based on the encrypted third value.

公开(公告)号：US20240070022A1

公开(公告)日：2024-02-29

申请号：US17897186

申请日：2022-08-28

Applicant: Micron Technology, Inc.

Inventor： Steffen Buch

IPC: G06F11/10 ,  G06F11/07

CPC classification number: G06F11/1068 ,  G06F11/0763 ,  G06F11/0772

Abstract: Methods, apparatuses, and non-transitory machine-readable media associated with a data inversion and unidirectional error detection are described. An apparatus for data inversion and unidirectional error detection can include a memory device and a processing device communicatively coupled to the memory device. The processing device can be configured to encode a plurality of binary data bits in an information word, encode the information word using a unidirectional error detecting code, write the encoded information word to the memory device, read the encoded information word from the memory device, and detect an error in the information word using a unidirectional error detecting code. The encoding can include inverting the plurality of binary data bits and adding an inversion data bit to the information word.

公开(公告)号：US20240028247A1

公开(公告)日：2024-01-25

申请号：US17868041

申请日：2022-07-19

Applicant: Micron Technology, Inc.

Inventor： Steffen Buch ,  Thomas Hein

IPC: G06F3/06

CPC classification number: G06F3/0655 ,  G06F3/0604 ,  G06F3/0679

Abstract: Methods, systems, and devices for efficient error signaling by memory are described. When executing a read operation, a memory device may perform an error control operation to detect errors in data associated with the read operation and transmit signaling indicating the data. The memory device may transmit signaling indicating a first or second value of an indicator of a combination error: the first value indicating that an error was detected in the data during the error control operation or a non-driven condition for transmitting the signaling indicating the data, and the second value indicating that no errors were detected in the data during the error control operation and that the read operation has been executed. The memory device may additionally store a value in a register indicating whether an indicated combination error corresponds to errors being detected in the data, a non-driven condition, or both.

公开(公告)号：US20220057960A1

公开(公告)日：2022-02-24

申请号：US17396529

申请日：2021-08-06

Applicant: Micron Technology, Inc.

Inventor： Aaron P. Boehm ,  Steffen Buch ,  Lance W. Dover

IPC: G06F3/06

Abstract: Methods, systems, and devices for host verification for a memory device are described. A memory device may receive a first value from a host device that is associated with an identification of the host device after an event. The memory device may transmit a second value to the host device that is based on the first value and comprises a random set of bits. The memory device may receive from the host device data or a command that comprises an encrypted third value that is based at least in part on the second value and a secret shared between the host device and the memory device. The memory device may also enable a functionality of the memory device based on the encrypted third value.