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公开(公告)号：US20240289220A1
公开(公告)日：2024-08-29
申请号：US18658754
申请日：2024-05-08
发明人： Steffen Buch , Thomas Hein
CPC分类号： G06F11/1068 , G06F11/076 , G06F11/0772 , G06F11/0787
摘要： Methods, systems, and devices for memory operations are described. A first code for detecting one or more errors in a first set of bits of data and a second code for detecting one or more errors in a second set of bits of data may be generated. The first set of bits and the second set of bits may be transmitted over a channel between a memory device and a host device in an interleaved pattern. The first code and the second code may also be transmitted over the channel. The first set of bits and the second set of bits may be deinterleaved by the receiving device. The first set of bits and the second set of bits may also be processed by the receiving device using the first code and the second code.
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公开(公告)号：US20240095119A1
公开(公告)日：2024-03-21
申请号：US18211472
申请日：2023-06-19
CPC分类号： G06F11/1044 , G06F11/1016 , G06F11/1028 , G11C29/42
摘要： Systems, apparatuses, and methods for transmission failure feedback associated with a memory device are described. A memory device may detect errors in received data and transmit an indication of the error when detected. The memory device may receive data and checksum information for the data from a controller. The memory device may generate a checksum for the received data and may detect transmission errors. The memory device may transmit an indication of detected errors to the controller, and the indication may be transmitted using a line that is different than an error detection code (EDC) line. A low-speed tracking clock signal may also be transmitted by the memory device over a line different than the EDC line. The memory device may transmit a generated checksum to the controller with a time offset applied to the checksum signaled over the EDC line.
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公开(公告)号：US11870616B2
公开(公告)日：2024-01-09
申请号：US17157815
申请日：2021-01-25
发明人： Stefan Dietrich , Natalija Jovanovic , Ronny Schneider , Martin Brox , Thomas Hein , Michael Dieter Richter
CPC分类号： H04L25/4917 , H04L1/0003
摘要： Methods, systems, and devices for postamble for multi-level signal modulation are described. One or more channels of a bus may be driven with a multi-level signal having at least two (2) distinct signal levels. After driving the bus with the multi-level signal, at least one (1) of the channels may be terminated. In some examples, the channel may be terminated to a relatively high signal level. Before termination, the channel may be driven with a postamble having an intermediate signal level. Driving the channel to an intermediate signal level before terminating the channel (e.g., to a high signal level) may avoid maximum transitions of the signal. For example, transitions between a lowest potential signal level and the high signal level (e.g., the termination level) may be avoided.
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公开(公告)号：US20230386527A1
公开(公告)日：2023-11-30
申请号：US18202584
申请日：2023-05-26
CPC分类号： G11C5/147 , G11C5/148 , G11C11/56 , G11C7/1096 , G11C7/1063 , G11C7/109 , G11C7/1069 , G11C11/221 , G11C11/2273 , G11C11/5657
摘要： Methods, systems, and devices for drive strength calibration for multi-level signaling are described. A driver may be configured to have an initial drive strength and to drive an output pin of a transmitting device toward an intermediate voltage level of a multi-level modulation scheme, where the output pin is coupled with a receiving device via a channel. The receiving device may generate, and the transmitting device may receive, a feedback signal indicating a relationship between the resulting voltage of the channel and an value for the intermediate voltage level. The transmitting device may determine and configure the driver to use an adjusted drive strength for the intermediate voltage level based on the feedback signal. The driver may be calibrated (e.g., independently) for each intermediate voltage level of the multi-level modulation scheme. Further, the driver may be calibrated for the associated channel.
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公开(公告)号：US11621033B2
公开(公告)日：2023-04-04
申请号：US17145066
申请日：2021-01-08
发明人： Martin Brox , Thomas Hein , Stefan Dietrich , Natalija Jovanovic , Ronny Schneider , Michael Dieter Richter
IPC分类号： G11C11/4076 , H01L27/00 , H04L27/00 , G11C7/10 , G11C11/4093
摘要： Methods, systems, and devices for techniques for low power operation are described. A device may be configurable to operate in a first mode and a second mode, where the first mode may include transmitting using a first modulation scheme having two logic levels and the second mode may include transmitting using a second modulation scheme having three or more (e.g., four) logic levels. The device may identify a data symbol for transmission and select, from the first mode and the second mode, the first modulation scheme for the transmission. In some example, the device may determine which of the two modes to select based on a value stored at a mode register. Here, the value stored by the mode register may indicate to utilize the first modulation scheme associated with the first mode. Thus, the device may transmit the data symbol by a signal modulated by the first modulation scheme.
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公开(公告)号：US11620241B2
公开(公告)日：2023-04-04
申请号：US17393819
申请日：2021-08-04
摘要： Methods, systems, and devices for dynamically configuring transmission lines of a bus between two electronic devices (e.g., a controller and memory device) are described. A first device may determine a quantity of bits (e.g., data bits, control bits) to be communicated with a second device over a data bus. The first device may partition the data bus into a first set of transmission lines (e.g., based on the quantity of data bits) and a second set of transmission lines (e.g., based on the quantity of control bits). The first device may communicate the quantity of data bits over the first set of transmission lines and communicate the quantity of control bits over the second set of transmission lines. In some cases, the first device may repartition the data bus based on different quantities of data bits and control bits to be communicated with the second device at a different time.
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公开(公告)号：US11579988B2
公开(公告)日：2023-02-14
申请号：US17376728
申请日：2021-07-15
摘要： Methods, systems, and devices for reporting control information errors are described. A state of a memory array may be monitored during operation. After detecting an error (e.g., in received control information), the memory device may enter a first state (e.g., a locked state) and may indicate to a host device that an error was detected, the state of the memory array before the error was detected, and/or at least a portion of a control signal carrying the received control information. The host device may diagnose a cause of the error based on receiving the indication of the error and/or the copy of the control signal. After identifying and/or resolving the cause of the error, the host device may transmit one or more commands (e.g., unlocking the memory device and returning the memory array to the original state) based on receiving the original state from the memory device.
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公开(公告)号：US20220365845A1
公开(公告)日：2022-11-17
申请号：US17732289
申请日：2022-04-28
发明人： Steffen Buch , Thomas Hein
摘要： Methods, systems, and devices for memory operations are described. A first code for detecting one or more errors in a first set of bits of data and a second code for detecting one or more errors in a second set of bits of data may be generated. The first set of bits and the second set of bits may be transmitted over a channel between a memory device and a host device in an interleaved pattern. The first code and the second code may also be transmitted over the channel. The first set of bits and the second set of bits may be deinterleaved by the receiving device. The first set of bits and the second set of bits may also be processed by the receiving device using the first code and the second code.
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公开(公告)号：US20220334915A1
公开(公告)日：2022-10-20
申请号：US17857700
申请日：2022-07-05
发明人： Martin Brox , Peter Mayer , Wolfgang Anton Spirkl , Thomas Hein , Michael Dieter Richter , Timothy M. Hollis , Roy E. Greeff
摘要： Methods, systems, and devices for channel modulation for a memory device are described. A system may include a memory device and a host device coupled with the memory device. The system may be configured to communicate a first signal modulated using a first modulation scheme and communicate a second signal that is based on the first signal and that is modulated using a second modulation scheme. The first modulation scheme may include a first quantity of voltage levels that span a first range of voltages, and the second modulation scheme may include a second quantity of voltage levels that span a second range of voltages different than (e.g., smaller than) the first range of voltages. The first signal may include write data carried over a data channel, and the second signal may include error detection information based on the write data that is carried over an error detection channel.
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公开(公告)号：US11409595B2
公开(公告)日：2022-08-09
申请号：US16744025
申请日：2020-01-15
发明人： Martin Brox , Peter Mayer , Wolfgang Anton Spirkl , Thomas Hein , Michael Dieter Richter , Timothy M. Hollis , Roy E. Greeff
摘要： Methods, systems, and devices for channel modulation for a memory device are described. A system may include a memory device and a host device coupled with the memory device. The system may be configured to communicate a first signal modulated using a first modulation scheme and communicate a second signal that is based on the first signal and that is modulated using a second modulation scheme. The first modulation scheme may include a first quantity of voltage levels that span a first range of voltages, and the second modulation scheme may include a second quantity of voltage levels that span a second range of voltages different than (e.g., smaller than) the first range of voltages. The first signal may include write data carried over a data channel, and the second signal may include error detection information based on the write data that is carried over an error detection channel.
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