公开(公告)号：US20210223999A1

公开(公告)日：2021-07-22

申请号：US17223684

申请日：2021-04-06

Applicant: Micron Technology, Inc.

Inventor： Patrick A. La Fratta ,  Robert Walker

IPC: G06F3/06

Abstract: Commands in a command queue are received and scheduled. For each of the commands, scheduling includes determining an age of a command based on an entrance time of the command in the command queue. When the age of the command satisfies a first threshold, marking all other commands in the command queue as not issuable when the command is a deterministic command, and marking all other commands in the command queue as not issuable when the command is a non-deterministic command and the intermediate command queue is not empty. Scheduling the command further includes determining whether the command is a read command and marking the command as not issuable when the command is a non-deterministic read command and the intermediate command queue is empty.

公开(公告)号：US20200272562A1

公开(公告)日：2020-08-27

申请号：US16285909

申请日：2019-02-26

Applicant: Micron Technology, Inc.

Inventor： Patrick A. La Fratta ,  Robert Walker ,  Chandrasekhar Nagarajan

IPC: G06F12/06 ,  G06F12/04

Abstract: A system generating, using a first addressable unit address decoder, a first addressable unit address based on an input address, an interleaving factor, and a number of first addressable units. The system then generating, using an internal address decoder, an internal address based on the input address, the interleaving factor, and the number of first addressable units. Generating the internal address includes: determining a lower address value by extracting lower bits of the internal address, determining an upper address value by extracting upper bits of the internal address, and adding the lower address value to the upper address value to generate the internal address. Using an internal power-of-two address boundary decoder and the internal address, the system then generating a second addressable unit address, a third addressable unit address, a fourth addressable unit address, and a fifth addressable unit address.

公开(公告)号：US20200264804A1

公开(公告)日：2020-08-20

申请号：US16280607

申请日：2019-02-20

Applicant: Micron Technology, Inc.

Inventor： Patrick A. La Fratta ,  Robert Walker

IPC: G06F3/06

Abstract: Commands in a command queue are received and scheduled. For each of the commands, scheduling includes determining an age of a command based on an entrance time of the command in the command queue. When the age of the command satisfies a first threshold, marking all other commands in the command queue as not issuable when the command is a deterministic command, and marking all other commands in the command queue as not issuable when the command is a non-deterministic command and the intermediate command queue is not empty. Scheduling the command further includes determining whether the command is a read command and marking the command as not issuable when the command is a non-deterministic read command and the intermediate command queue is empty.

公开(公告)号：US20200159437A1

公开(公告)日：2020-05-21

申请号：US16195127

申请日：2018-11-19

Applicant: Micron Technology, Inc.

Inventor： Robert M. Walker ,  Paul Rosenfeld ,  Patrick A. La Fratta

IPC: G06F3/06

Abstract: Apparatuses and methods for performing data migration operations are disclosed. An apparatus may include at least two interfaces, a first interface supporting data migration operations and a second interface supporting access operations associated with a host device. In some cases, the access operations may be a signal or protocol according to an industry standard or specification (e.g., a DRAM interface specification). The second interface may facilitate supporting industry standard applications, while the first interface supporting data migration operations may provide improved bandwidth for migrating data within the apparatus. The apparatus may include a buffer coupled with the interface and a bank cluster including two or more banks of memory cells. When a host device addresses a bank of the bank cluster, the apparatus may perform one or more data migration operations using the buffer and a different bank of the bank cluster.

公开(公告)号：US20200159436A1

公开(公告)日：2020-05-21

申请号：US16195071

申请日：2018-11-19

Applicant: Micron Technology, Inc.

Inventor： Robert M. Walker ,  Paul Rosenfeld ,  Patrick A. La Fratta

IPC: G06F3/06

Abstract: Apparatuses and methods for performing data migration operations are disclosed. An apparatus may include at least two interfaces, a first interface supporting data migration operations and a second interface supporting access operations associated with a host device. In some cases, the access operations may be a signal or protocol according to an industry standard or specification (e.g., a DRAM interface specification). The second interface may facilitate supporting industry standard applications, while the first interface supporting data migration operations may provide improved bandwidth for migrating data within the apparatus. The apparatus may include a buffer coupled with the interface and a bank cluster including two or more banks of memory cells. When a host device addresses a bank of the bank cluster, the apparatus may perform one or more data migration operations using the buffer and a different bank of the bank cluster.

公开(公告)号：US10460773B2

公开(公告)日：2019-10-29

申请号：US16047949

申请日：2018-07-27

Applicant: Micron Technology, Inc.

Inventor： Patrick A. La Fratta

IPC: G11C7/06 ,  G11C7/10

Abstract: The present disclosure includes apparatuses and methods related to converting a mask to an index. An example apparatus comprises an array of memory cells and periphery logic configured to: generate an indicator mask by resetting, in response to a first control signal, a second digit of a mask different from a first digit of the mask that is set; and convert, in response to a second control signal, a digit position in the indicator mask of the first digit that is set to an identifier value as an index.

公开(公告)号：US10037786B2

公开(公告)日：2018-07-31

申请号：US15687813

申请日：2017-08-28

Applicant: Micron Technology, Inc.

Inventor： Patrick A. La Fratta

IPC: G11C7/06 ,  G11C7/10

CPC classification number: G11C7/06 ,  G11C7/1006

Abstract: The present disclosure includes apparatuses and methods related to converting a mask to an index. An example apparatus comprises an array of memory cells and periphery logic configured to: generate an indicator mask by resetting, in response to a first control signal, a second digit of a mask different from a first digit of the mask that is set; and convert, in response to a second control signal, a digit position in the indicator mask of the first digit that is set to an identifier value as an index.

公开(公告)号：US20160371033A1

公开(公告)日：2016-12-22

申请号：US15184516

申请日：2016-06-16

Applicant: Micron Technology, Inc.

Inventor： Patrick A. La Fratta ,  James J. Shawver

IPC: G06F3/06 ,  G11C7/10

CPC classification number: G06F3/0655 ,  G06F3/061 ,  G06F3/0673 ,  G11C7/1006 ,  G11C11/4076 ,  G11C11/4091 ,  G11C11/4097

Abstract: The present disclosure describes data transfer in a memory device from sensing circuitry to controller. An example apparatus includes a controller coupled to a memory device. The controller is configured to execute a command to transfer data from a latch component to a register file in the controller. The memory device includes an array of memory cells and the latch component is coupled to rows of the array via a plurality of columns of the memory cells. The latch component includes a latch selectably coupled to each of the columns and configured to implement the command to transfer the data. The memory device includes a data line to couple the latch component to the register file to transfer the data. The controller is configured to couple to the data line and the register file to perform a write operation on the transferred data to the register file in the controller.

Abstract translation: 本公开描述了存储器装置中从感测电路到控制器的数据传输。 示例性装置包括耦合到存储器件的控制器。 控制器被配置为执行将数据从锁存器组件传送到控制器中的寄存器文件的命令。 存储器件包括存储器单元的阵列，并且锁存器部件经由存储器单元的多个列耦合到阵列的行。 锁存部件包括可选地耦合到每个列的锁存器，并被配置为实现传送数据的命令。 存储器件包括用于将锁存器组件耦合到寄存器文件以传送数据的数据线。 控制器被配置为耦合到数据线和寄存器文件以对传送的数据执行写入操作到控制器中的寄存器文件。

公开(公告)号：US11625197B2

公开(公告)日：2023-04-11

申请号：US17498415

申请日：2021-10-11

Applicant: Micron Technology, Inc.

Inventor： Patrick A. La Fratta ,  Robert Walker

IPC: G06F3/06

Abstract: Initialization is performed based on the commands received at the command queue. To perform initialization, a bank touch count list that includes a list of banks being accessed by the commands and a bank touch count for each of the banks in the list is updated. The bank touch count identifies the number of commands accessing each of the banks. The bank touch count list is updated by assigning a bank priority rank to each of the banks based on their bank touch count, respectively. Once initialized, the commands in the command queue are scheduled by inserting each of the commands into priority queues based on the bank touch count list.

公开(公告)号：US11567700B2

公开(公告)日：2023-01-31

申请号：US17223684

申请日：2021-04-06

Applicant: Micron Technology, Inc.

Inventor： Patrick A. La Fratta ,  Robert Walker

IPC: G06F3/06

Abstract: Commands in a command queue are received and scheduled. For each of the commands, scheduling includes determining an age of a command based on an entrance time of the command in the command queue. When the age of the command satisfies a first threshold, marking all other commands in the command queue as not issuable when the command is a deterministic command, and marking all other commands in the command queue as not issuable when the command is a non-deterministic command and the intermediate command queue is not empty. Scheduling the command further includes determining whether the command is a read command and marking the command as not issuable when the command is a non-deterministic read command and the intermediate command queue is empty.