公开(公告)号：US20210193569A1

公开(公告)日：2021-06-24

申请号：US16720579

申请日：2019-12-19

Applicant: NXP USA, Inc.

Inventor： Vikas Shilimkar ,  Kevin Kim ,  Charles John Lessard ,  Humayun Kabir

IPC: H01L23/522 ,  H01L23/528

Abstract: A transistor includes a semiconductor substrate having a first terminal and a second terminal. An interconnect structure is formed on an upper surface of the semiconductor substrate, the interconnect structure being formed of multiple layers of dielectric material and electrically conductive material. The electrically conductive material of the interconnect structure includes a pillar in electrical contact with the first terminal, a first runner electrically connected to the pillar, a tap interconnect in electrical contact with the second terminal, a second runner electrically connected to the tap interconnect, a shield structure positioned between the pillar and the tap interconnect, and a shield runner electrically connected to the shield structure, the shield runner overlying the second runner in a direction perpendicular to the upper surface of the semiconductor substrate.

公开(公告)号：US20210050820A1

公开(公告)日：2021-02-18

申请号：US16541551

申请日：2019-08-15

Applicant: NXP USA, Inc.

Inventor： Ibrahim Khalil ,  Hussain Hasanali Ladhani ,  Humayun Kabir

IPC: H03F1/02 ,  H01L23/66 ,  H03F1/56 ,  H03F3/195

Abstract: A multiple-path amplifier (e.g., a Doherty amplifier) includes first and second amplifier input terminals and an amplifier output terminal integrally-formed with a semiconductor die, and at least two amplifier cells positioned adjacent to each other between the amplifier input terminals and the amplifier output terminal. Each amplifier cell includes first and second transistors (e.g., field effect transistors) integrally-formed with the semiconductor die, where the first and second transistors each include a transistor input (e.g., a gate terminal) and a transistor output (e.g., a drain terminal). The first transistor input is coupled to the first amplifier input terminal, and the second transistor input is coupled to the second amplifier input terminal. A combining node is coupled to the second transistor output and to the amplifier output terminal, and a first phase shift element (e.g., an inductor) is electrically connected between the first transistor output and the combining node.