公开(公告)号：US10593619B1

公开(公告)日：2020-03-17

申请号：US16114468

申请日：2018-08-28

Applicant: NXP USA, Inc.

Inventor： Ibrahim Khalil ,  Charles John Lessard ,  Damon G. Holmes ,  Hernan Rueda

IPC: H01L23/522 ,  H01L21/3205 ,  H01L21/768 ,  H01L21/8234 ,  H01L23/528 ,  H01L23/66 ,  H01L23/482 ,  H01L23/58 ,  H01L27/02

Abstract: A transistor includes a semiconductor substrate having a first terminal and a gate region, and an interconnect structure formed of multiple layers of dielectric and electrically material on an upper surface of the semiconductor substrate. The electrically conductive material includes first and second layers, the second layer being spaced apart from the first layer by a first dielectric layer of the dielectric material, the first layer residing closest to the upper surface of the semiconductor substrate relative to the second layer. The interconnect structure includes a pillar formed from the conductive material. The pillar is in electrical contact with the first terminal, the pillar extends through the dielectric material, and the pillar includes a pillar segment in the first layer of the conductive material. The interconnect structure also includes a shield structure in the first layer of the conductive material and positioned between the pillar segment and the gate region.

公开(公告)号：US20220068767A1

公开(公告)日：2022-03-03

申请号：US17007175

申请日：2020-08-31

Applicant: NXP USA, Inc.

Inventor： Ibrahim Khalil ,  Charles John Lessard ,  Jeffrey Kevin Jones

IPC: H01L23/482 ,  H01L27/088 ,  H01L23/433

Abstract: Radio frequency (RF) power dies having flip-chip architectures are disclosed, as are power amplifier modules (PAMs) containing such RF power dies. Embodiment of the PAM include a module substrate and an RF power die, which is mounted to a surface of the module substrate in an inverted orientation. The RF power die includes, in turn, a die body having a frontside and an opposing backside, a transistor having active regions formed in the die body, and a frontside layer system formed over the die body frontside. The frontside layer system contains patterned metal layers defining first, second, and third branched electrode structures, which are electrically coupled to the active regions of the transistor. A frontside input/output interface is formed in an outer terminal portion of the frontside layer system and contains first, second, and third bond pads electrically coupled to the first, second, and third branched electrode structures, respectively.

公开(公告)号：US11430743B1

公开(公告)日：2022-08-30

申请号：US17223410

申请日：2021-04-06

Applicant: NXP USA, Inc.

Inventor： Humayun Kabir ,  Michele Lynn Miera ,  Charles John Lessard ,  Ibrahim Khalil

IPC: H01L23/522 ,  H01L21/768 ,  H01L23/552 ,  H01L23/535 ,  H01L29/78

Abstract: A transistor includes a semiconductor substrate having first and second terminals. An interconnect structure, on an upper surface of the substrate, is formed of layers of dielectric material and electrically conductive material. The conductive material includes a first pillar connected with the first terminal, a second pillar connected with the second terminal, and a shield system between the first and second pillars. The shield system includes forked structures formed in at least two conductive layers of the interconnect structure and at least partially surrounding segments of the second pillar. The shield system may additionally include shield traces formed in a first conductive layer positioned between gate fingers and the first pillars and/or the shield system may include shield runners that are located in an electrically conductive layer that is below a topmost electrically conductive layer with the first pillar being connected to a runner in the topmost conductive layer.

公开(公告)号：US11302609B2

公开(公告)日：2022-04-12

申请号：US17007175

申请日：2020-08-31

Applicant: NXP USA, Inc.

Inventor： Ibrahim Khalil ,  Charles John Lessard ,  Jeffrey Kevin Jones

IPC: H01L23/482 ,  H01L23/433 ,  H01L27/088

Abstract: Radio frequency (RF) power dies having flip-chip architectures are disclosed, as are power amplifier modules (PAMs) containing such RF power dies. Embodiment of the PAM include a module substrate and an RF power die, which is mounted to a surface of the module substrate in an inverted orientation. The RF power die includes, in turn, a die body having a frontside and an opposing backside, a transistor having active regions formed in the die body, and a frontside layer system formed over the die body frontside. The frontside layer system contains patterned metal layers defining first, second, and third branched electrode structures, which are electrically coupled to the active regions of the transistor. A frontside input/output interface is formed in an outer terminal portion of the frontside layer system and contains first, second, and third bond pads electrically coupled to the first, second, and third branched electrode structures, respectively.

公开(公告)号：US10147686B1

公开(公告)日：2018-12-04

申请号：US15715623

申请日：2017-09-26

Applicant: NXP USA, INC.

Inventor： Charles John Lessard ,  Damon G. Holmes ,  David Cobb Burdeaux ,  Hernan Rueda ,  Ibrahim Khalil

IPC: H01L23/58 ,  H01L23/552 ,  H01L23/66 ,  H01L23/48 ,  H01L23/528 ,  H01L23/522 ,  H01L21/768 ,  H01L29/78 ,  H03F1/02 ,  H03F3/195

Abstract: A transistor includes a semiconductor substrate having an intrinsic active device, a first terminal, and a second terminal. The transistor also includes an interconnect structure formed of layers of dielectric material and electrically conductive material on the semiconductor substrate. The interconnect structure includes a pillar, a tap interconnect, and a shield structure positioned between the pillar and the tap interconnect formed from the electrically conductive material and extending through the dielectric material. The pillar contacts the first terminal and connects to a first runner. The tap interconnect contacts the second terminal and connects to a second runner. The shield structure includes a base segment, a first leg, and a second leg extending from opposing ends of the base segment, wherein the first and second legs extend from opposing ends of the base segment in a direction that is antiparallel to a length of the base segment.

公开(公告)号：US12237257B2

公开(公告)日：2025-02-25

申请号：US17448709

申请日：2021-09-24

Applicant: NXP USA, Inc.

Inventor： Vikas Shilimkar ,  Kevin Kim ,  Charles John Lessard ,  Humayun Kabir

IPC: H01L23/52 ,  H01L23/522 ,  H01L23/528

Abstract: A transistor includes a semiconductor substrate having a first terminal and a second terminal. An interconnect structure is formed on an upper surface of the semiconductor substrate, the interconnect structure being formed of multiple layers of dielectric material and electrically conductive material. The electrically conductive material of the interconnect structure includes a pillar in electrical contact with the first terminal, a first runner electrically connected to the pillar, a tap interconnect in electrical contact with the second terminal, a second runner electrically connected to the tap interconnect, a shield structure positioned between the pillar and the tap interconnect, and a shield runner electrically connected to the shield structure, the shield runner overlying the second runner in a direction perpendicular to the upper surface of the semiconductor substrate.

公开(公告)号：US20220013451A1

公开(公告)日：2022-01-13

申请号：US17448709

申请日：2021-09-24

Applicant: NXP USA, Inc.

Inventor： Vikas Shilimkar ,  Kevin Kim ,  Charles John Lessard ,  Humayun Kabir

IPC: H01L23/522 ,  H01L23/528

Abstract: A transistor includes a semiconductor substrate having a first terminal and a second terminal. An interconnect structure is formed on an upper surface of the semiconductor substrate, the interconnect structure being formed of multiple layers of dielectric material and electrically conductive material. The electrically conductive material of the interconnect structure includes a pillar in electrical contact with the first terminal, a first runner electrically connected to the pillar, a tap interconnect in electrical contact with the second terminal, a second runner electrically connected to the tap interconnect, a shield structure positioned between the pillar and the tap interconnect, and a shield runner electrically connected to the shield structure, the shield runner overlying the second runner in a direction perpendicular to the upper surface of the semiconductor substrate.

公开(公告)号：US11177207B2

公开(公告)日：2021-11-16

申请号：US16720579

申请日：2019-12-19

Applicant: NXP USA, Inc.

Inventor： Vikas Shilimkar ,  Kevin Kim ,  Charles John Lessard ,  Humayun Kabir

IPC: H01L23/522 ,  H01L23/528

Abstract: A transistor includes a semiconductor substrate having a first terminal and a second terminal. An interconnect structure is formed on an upper surface of the semiconductor substrate, the interconnect structure being formed of multiple layers of dielectric material and electrically conductive material. The electrically conductive material of the interconnect structure includes a pillar in electrical contact with the first terminal, a first runner electrically connected to the pillar, a tap interconnect in electrical contact with the second terminal, a second runner electrically connected to the tap interconnect, a shield structure positioned between the pillar and the tap interconnect, and a shield runner electrically connected to the shield structure, the shield runner overlying the second runner in a direction perpendicular to the upper surface of the semiconductor substrate.

公开(公告)号：US20210193569A1

公开(公告)日：2021-06-24

申请号：US16720579

申请日：2019-12-19

Applicant: NXP USA, Inc.

Inventor： Vikas Shilimkar ,  Kevin Kim ,  Charles John Lessard ,  Humayun Kabir

IPC: H01L23/522 ,  H01L23/528

Abstract: A transistor includes a semiconductor substrate having a first terminal and a second terminal. An interconnect structure is formed on an upper surface of the semiconductor substrate, the interconnect structure being formed of multiple layers of dielectric material and electrically conductive material. The electrically conductive material of the interconnect structure includes a pillar in electrical contact with the first terminal, a first runner electrically connected to the pillar, a tap interconnect in electrical contact with the second terminal, a second runner electrically connected to the tap interconnect, a shield structure positioned between the pillar and the tap interconnect, and a shield runner electrically connected to the shield structure, the shield runner overlying the second runner in a direction perpendicular to the upper surface of the semiconductor substrate.

公开(公告)号：US20200075479A1

公开(公告)日：2020-03-05

申请号：US16114468

申请日：2018-08-28

Applicant: NXP USA, Inc.

Inventor： Ibrahim Khalil ,  Charles John Lessard ,  Damon G. Holmes ,  Hernan Rueda

IPC: H01L23/522 ,  H01L21/3205 ,  H01L21/768 ,  H01L21/8234 ,  H01L23/482 ,  H01L23/528 ,  H01L23/66

Abstract: A transistor includes a semiconductor substrate having a first terminal and a gate region, and an interconnect structure formed of multiple layers of dielectric and electrically material on an upper surface of the semiconductor substrate. The electrically conductive material includes first and second layers, the second layer being spaced apart from the first layer by a first dielectric layer of the dielectric material, the first layer residing closest to the upper surface of the semiconductor substrate relative to the second layer. The interconnect structure includes a pillar formed from the conductive material. The pillar is in electrical contact with the first terminal, the pillar extends through the dielectric material, and the pillar includes a pillar segment in the first layer of the conductive material. The interconnect structure also includes a shield structure in the first layer of the conductive material and positioned between the pillar segment and the gate region.