公开(公告)号：US20230207675A1

公开(公告)日：2023-06-29

申请号：US17561793

申请日：2021-12-24

Applicant: NXP USA, INC.

Inventor： Bernhard Grote ,  Humayun Kabir ,  Bruce McRae Green ,  Ibrahim Khalil

IPC: H01L29/778 ,  H01L29/423 ,  H01L29/40 ,  H01L29/66

CPC classification number: H01L29/7786 ,  H01L29/42376 ,  H01L29/402 ,  H01L29/66462

Abstract: A semiconductor device includes a semiconductor substrate, a first dielectric layer disposed over the upper surface of the semiconductor substrate, a second dielectric layer disposed over the first dielectric layer, a third dielectric layer disposed over the second dielectric layer, a lower opening formed in the first dielectric layer, an upper opening formed in the second dielectric layer and the third dielectric layer, wherein at least a portion of the upper opening overlaps a portion of the lower opening, and a control electrode formed within at least a portion of the lower opening and within a portion of the upper opening, wherein a portion of the control electrode is formed over the third dielectric layer.

公开(公告)号：US11108361B2

公开(公告)日：2021-08-31

申请号：US16541551

申请日：2019-08-15

Applicant: NXP USA, Inc.

Inventor： Ibrahim Khalil ,  Hussain Hasanali Ladhani ,  Humayun Kabir

IPC: H03F3/68 ,  H03F1/02 ,  H01L23/66 ,  H03F1/56 ,  H03F3/195 ,  H03F3/21

Abstract: A multiple-path amplifier (e.g., a Doherty amplifier) includes first and second amplifier input terminals and an amplifier output terminal integrally-formed with a semiconductor die, and at least two amplifier cells positioned adjacent to each other between the amplifier input terminals and the amplifier output terminal. Each amplifier cell includes first and second transistors (e.g., field effect transistors) integrally-formed with the semiconductor die, where the first and second transistors each include a transistor input (e.g., a gate terminal) and a transistor output (e.g., a drain terminal). The first transistor input is coupled to the first amplifier input terminal, and the second transistor input is coupled to the second amplifier input terminal. A combining node is coupled to the second transistor output and to the amplifier output terminal, and a first phase shift element (e.g., an inductor) is electrically connected between the first transistor output and the combining node.

公开(公告)号：US11804527B2

公开(公告)日：2023-10-31

申请号：US17376026

申请日：2021-07-14

Applicant: NXP USA, Inc.

Inventor： Vikas Shilimkar ,  Kevin Kim ,  Daniel Joseph Lamey ,  Bruce McRae Green ,  Ibrahim Khalil ,  Humayun Kabir

IPC: H01L29/417 ,  H01L29/778 ,  H01L23/00 ,  H01L29/40 ,  H01L23/48

CPC classification number: H01L29/41775 ,  H01L23/481 ,  H01L24/05 ,  H01L29/401 ,  H01L29/7786 ,  H01L2224/04042

Abstract: A transistor includes a source contact connected to a Through-Silicon Via (TSV). A drain contact is connected to a first pad. A gate structure is interposed between the source contact and the drain contact. A second pad is connected to the gate structure, the second pad comprising a first side diametrically opposed to a second side, and a third side interposed therebetween, the source contact proximal to the third side, a first portion of the first side and a second portion of the second side.

公开(公告)号：US11430743B1

公开(公告)日：2022-08-30

申请号：US17223410

申请日：2021-04-06

Applicant: NXP USA, Inc.

Inventor： Humayun Kabir ,  Michele Lynn Miera ,  Charles John Lessard ,  Ibrahim Khalil

IPC: H01L23/522 ,  H01L21/768 ,  H01L23/552 ,  H01L23/535 ,  H01L29/78

Abstract: A transistor includes a semiconductor substrate having first and second terminals. An interconnect structure, on an upper surface of the substrate, is formed of layers of dielectric material and electrically conductive material. The conductive material includes a first pillar connected with the first terminal, a second pillar connected with the second terminal, and a shield system between the first and second pillars. The shield system includes forked structures formed in at least two conductive layers of the interconnect structure and at least partially surrounding segments of the second pillar. The shield system may additionally include shield traces formed in a first conductive layer positioned between gate fingers and the first pillars and/or the shield system may include shield runners that are located in an electrically conductive layer that is below a topmost electrically conductive layer with the first pillar being connected to a runner in the topmost conductive layer.

公开(公告)号：US20240339409A1

公开(公告)日：2024-10-10

申请号：US18296786

申请日：2023-04-06

Applicant: NXP USA, Inc.

Inventor： Humayun Kabir ,  Ibrahim Khalil

IPC: H01L23/538 ,  H01L23/66

CPC classification number: H01L23/5384 ,  H01L23/5386 ,  H01L23/66 ,  H01L2223/6616

Abstract: A transistor includes a semiconductor die with an active region and one or more non-active regions that do not overlap or overlie the active region. The transistor further includes a group of multiple transistor fingers in the active region. One or more source vias are located adjacent to sides of the group of transistor fingers. One or more source manifolds are located in the non-active region(s), and the source manifold(s) electrically connect the source via(s) with at least one source region of the multiple transistor fingers.

公开(公告)号：US20230369205A1

公开(公告)日：2023-11-16

申请号：US17663181

申请日：2022-05-12

Applicant: NXP USA, Inc.

Inventor： Humayun Kabir ,  Ibrahim Khalil ,  Daniel Joseph Lamey ,  Yu-Ting David Wu

IPC: H01L23/528 ,  H01L25/10 ,  H01L29/417 ,  H01L27/088 ,  H01L21/8234 ,  H01L29/40 ,  H03K17/687

CPC classification number: H01L23/528 ,  H01L25/105 ,  H01L29/41725 ,  H01L27/088 ,  H01L21/823475 ,  H01L29/401 ,  H03K17/6871

Abstract: A device having a reference transistor fabricated within the same semiconductor substrate as a primary transistor (e.g., configured for use in a radiofrequency amplifier or other active circuit) has a shared metallization area coupled to a current terminal of both transistors configured to shield a control terminal of the reference transistor from coupling of alternating current interference from alternating currents within the primary transistor.

公开(公告)号：US20230197795A1

公开(公告)日：2023-06-22

申请号：US17645290

申请日：2021-12-20

Applicant: NXP USA, Inc.

Inventor： Bernhard Grote ,  Philippe Renaud ,  Humayun Kabir ,  Bruce McRae Green ,  Ibrahim Khalil

IPC: H01L29/40 ,  H01L29/20 ,  H01L29/778 ,  H01L21/76 ,  H01L21/765 ,  H01L29/66

CPC classification number: H01L29/401 ,  H01L29/2003 ,  H01L29/402 ,  H01L29/7786 ,  H01L21/7605 ,  H01L21/765 ,  H01L29/66462

Abstract: Placement of a field plate in a field-effect transistor is optimized by using multiple dielectric layers such that a first end of field plate is separated from a channel region of the transistor by a first set of one or more distinct dielectric material layers. A second end of the field plate overlies the channel region and a control electrode from which it is separated by the first set of dielectric layers and one or more additional dielectric layers. Relative positioning of the control electrode and the field plate are determined by a single processing step such that the field plate is self-aligned to the control electrode in order to reduce variations in transistor performance associated with manufacturing process variations.

公开(公告)号：US20230019549A1

公开(公告)日：2023-01-19

申请号：US17376026

申请日：2021-07-14

Applicant: NXP USA, Inc.

Inventor： Vikas Shilimkar ,  Kevin Kim ,  Daniel Joseph Lamey ,  Bruce McRae Green ,  Ibrahim Khalil ,  Humayun Kabir

IPC: H01L29/417 ,  H01L29/778 ,  H01L23/48 ,  H01L23/00 ,  H01L29/40

Abstract: A transistor includes a source contact connected to a Through-Silicon Via (TSV). A drain contact is connected to a first pad. A gate structure is interposed between the source contact and the drain contact. A second pad is connected to the gate structure, the second pad comprising a first side diametrically opposed to a second side, and a third side interposed therebetween, the source contact proximal to the third side, a first portion of the first side and a second portion of the second side.

公开(公告)号：US20220376060A1

公开(公告)日：2022-11-24

申请号：US17325995

申请日：2021-05-20

Applicant: NXP USA, INC.

Inventor： Bernhard Grote ,  Humayun Kabir ,  Ibrahim Khalil ,  Bruce McRae Green

IPC: H01L29/40 ,  H01L29/20 ,  H01L29/205 ,  H01L29/778 ,  H01L21/76 ,  H01L21/765 ,  H01L29/66

Abstract: An embodiment of a semiconductor device includes a semiconductor substrate, a first current-carrying electrode, and a second current-carrying electrode formed over the semiconductor, a control electrode formed over the semiconductor substrate between the first current carrying electrode and the second current carrying electrode, and a first dielectric layer disposed over the control electrode, and a second dielectric layer disposed over the first dielectric layer. A first opening is formed in the second dielectric layer, adjacent the control electrode and the second current-carrying electrode, having a first edge laterally adjacent to and nearer the second current-carrying electrode, and a second edge laterally adjacent to and nearer to the control electrode, and a conductive element formed over the first dielectric layer and within the first opening, wherein the portion of the conductive element formed within the first opening forms a first metal-insulator-semiconductor region within the first opening.

公开(公告)号：US10672703B2

公开(公告)日：2020-06-02

申请号：US16142713

申请日：2018-09-26

Applicant: NXP USA, Inc.

Inventor： Vikas Shilimkar ,  Kevin Kim ,  Hernan Rueda ,  Humayun Kabir

IPC: H01L23/522 ,  H01L23/528 ,  H01L23/31 ,  H01L21/56 ,  H01L27/088 ,  H01L21/8234

Abstract: A transistor includes a semiconductor substrate having an active device region formed therein and an interconnect structure on a first surface of the semiconductor substrate. The interconnect structure is formed of multiple layers of dielectric material and electrically conductive material. Drain and gate runners are formed in the interconnect structure. A shield structure extends above a second surface of the interconnect structure, the shield structure being positioned between the drain and gate runners.