公开(公告)号：US20240071960A1

公开(公告)日：2024-02-29

申请号：US17823116

申请日：2022-08-30

Applicant: NXP USA, Inc.

Inventor： Kevin Kim ,  Vikas Shilimkar ,  Joseph Gerard Schultz

IPC: H01L23/66 ,  H03F1/02 ,  H03F3/195 ,  H03F3/24

CPC classification number: H01L23/66 ,  H03F1/0288 ,  H03F3/195 ,  H03F3/245 ,  H01L2223/6611 ,  H01L2223/6622 ,  H01L2223/6655 ,  H03F2200/451

Abstract: A power amplifier device includes a substrate, a power transistor die, and one or more surface mount components. The substrate has substrate die contacts exposed at a first substrate surface, and additional substrate contacts exposed at a second substrate surface. The power transistor die includes an integrated transistor. The transistor includes a control terminal and a first current conducting terminal coupled, respectively, to first and second die contacts at the first die surface, and a second current conducting terminal coupled to a third die contact at a second die surface. The surface-mount components are connected to the additional substrate components, and the surface-mount components are electrically coupled through the substrate to the first and second die contacts. The power amplifier device also includes an encapsulation material layer covering the surface-mount components and the second substrate surface.

公开(公告)号：US10861774B2

公开(公告)日：2020-12-08

申请号：US16817235

申请日：2020-03-12

Applicant: NXP USA, INC.

Inventor： Audel Sanchez ,  Lakshminarayan Viswanathan ,  Vikas Shilimkar ,  Ramanujam Srinidhi Embar

IPC: H01L23/495 ,  H01L21/56 ,  H01L23/29 ,  H01L23/31 ,  H01L23/00 ,  H01L23/66 ,  H01L23/552 ,  H01L21/50

Abstract: Internally-shielded microelectronic packages having increased resistances to electromagnetic cross-coupling are disclosed, as are methods for fabricating such microelectronic packages. In embodiments, the internally-shielded microelectronic package includes a substrate having a frontside and a longitudinal axis. A first microelectronic device is mounted to the frontside of the substrate, while a second microelectronic device is further mounted to the frontside of the substrate and spaced from the first microelectronic device along the longitudinal axis. An internal shield structure includes or consists of a shield wall, which is positioned between the first and second microelectronic devices as taken along the longitudinal axis. The internal shield structure is at least partially composed of a magnetically-permeable material, which decreases electromagnetic cross-coupling between the first and second microelectronic devices during operation of the internally-shielded microelectronic package.

公开(公告)号：US12159845B2

公开(公告)日：2024-12-03

申请号：US17673636

申请日：2022-02-16

Applicant: NXP USA, Inc.

Inventor： Humayun Kabir ,  Vikas Shilimkar ,  Ibrahim Khalil ,  Kevin Kim

IPC: H01L23/58 ,  H01L23/00 ,  H01L23/48 ,  H01L23/66 ,  H01L29/06

Abstract: A device includes a semiconductor substrate, a source metallization over an active area of the semiconductor substrate, a through-substrate via electrically connected to the source metallization, and an input bond pad formed in the semiconductor substrate and spaced apart from the active area. The input bond pad is electrically connected to a set of gate structures. The device includes a first inductive coil over the semiconductor substrate between a first portion of the source metallization and a second portion of the source metallization and a first capacitor over the semiconductor substrate between the first portion of the source metallization and the second portion of the source metallization. The first inductive coil and the first capacitor are connected in series between the input bond pad and the through-substrate via.

公开(公告)号：US20230291369A1

公开(公告)日：2023-09-14

申请号：US17694142

申请日：2022-03-14

Applicant: NXP USA, Inc.

Inventor： Kevin Kim ,  Vikas Shilimkar ,  Lakshminarayan Viswanathan

IPC: H03F3/24 ,  H03F3/195 ,  H01L23/66

CPC classification number: H03F3/245 ,  H03F3/195 ,  H01L23/66 ,  H03F2200/451 ,  H01L2223/6655 ,  H01L2223/6616 ,  H01L2223/6611

Abstract: Power amplifier systems including field trapper structures are disclosed. In embodiments, the power amplifier system includes a printed circuit board (PCB), a power amplifier module (PAM), and a field trapper structure. The PAM includes, in turn, a topside radio frequency (RF) input terminal, topside RF output terminal, a PAM topside surface on which the topside RF input terminal and the topside RF output terminal are located. The PAM is mounted to the PCB in an inverted orientation such that the PAM topside surface is positioned adjacent and faces a module mount region provided on a frontside of the PCB. The field trapper structure includes a first field trapper patch, which extends parallel to the PCB frontside, is composed of an electrically-conductive material, and is located within or adjacent the module mount region in the thickness direction.

公开(公告)号：US20200098683A1

公开(公告)日：2020-03-26

申请号：US16142713

申请日：2018-09-26

Applicant: NXP USA, Inc.

Inventor： Vikas Shilimkar ,  Kevin Kim ,  Hernan Rueda ,  Humayun Kabir

IPC: H01L23/522 ,  H01L23/528 ,  H01L23/31 ,  H01L21/8234 ,  H01L21/56 ,  H01L27/088

Abstract: A transistor includes a semiconductor substrate having an active device region formed therein and an interconnect structure on a first surface of the semiconductor substrate. The interconnect structure is formed of multiple layers of dielectric material and electrically conductive material. Drain and gate runners are formed in the interconnect structure. A shield structure extends above a second surface of the interconnect structure, the shield structure being positioned between the drain and gate runners.

公开(公告)号：US20240072740A1

公开(公告)日：2024-02-29

申请号：US17823127

申请日：2022-08-30

Applicant: NXP USA, Inc.

Inventor： Kevin Kim ,  Vikas Shilimkar ,  Joseph Gerard Schultz

IPC: H03F3/24 ,  H01L23/66 ,  H03F1/02 ,  H03F3/195

CPC classification number: H03F3/245 ,  H01L23/66 ,  H03F1/0288 ,  H03F3/195 ,  H01L2223/6611 ,  H01L2223/6616 ,  H01L2223/6655 ,  H03F2200/451

Abstract: A power amplifier device includes first and second power transistor dies and a substrate. Each die includes an elongated bondpad and an integrated transistor with a terminal that is coupled to the elongated bondpad. The substrate is formed from a stack of multiple dielectric layers and multiple patterned conductive layers in an alternating arrangement, and a plurality of conductive vias electrically coupling portions of the conductive layers. The substrate includes elongated first and second die contacts exposed at a first substrate surface and connected to the first and second elongated bondpads, respectively. The substrate also includes a conductive structure connected between the first and second die contacts. The conductive structure is formed from portions of the patterned conductive layers and at least two vias of the plurality of conductive vias.

公开(公告)号：US20230361726A1

公开(公告)日：2023-11-09

申请号：US18176208

申请日：2023-02-28

Applicant: NXP USA, Inc.

Inventor： Joseph Gerard Schultz ,  Kevin Kim ,  Jeffrey Kevin Jones ,  Vikas Shilimkar ,  Olivier Lembeye

IPC: H03F3/19

CPC classification number: H03F3/19 ,  H03F2200/165 ,  H03F2200/171 ,  H03F2200/222 ,  H03F2200/387 ,  H03F2200/451

Abstract: An RF amplifier includes at least one harmonic trap filter with an array of shunt filter legs having a non-uniform resonance frequency distribution. The harmonic trap filter is configured to suppress frequencies in a suppression frequency range that includes harmonic frequencies of carrier frequencies in a range of carrier frequencies. Each of the shunt filter legs includes a capacitor and inductor coupled in series, and an intermediate node coupled between the capacitor and the inductor. Each intermediate node of the shunt filter leg is coupled to at least one other intermediate node of another shunt filter leg of the filter with a dampening resistor. Shunt filters at or near edges of the array are configured to have lower resonance frequencies than those at or near the center of the array to suppress excess current flow at edges of the RF amplifier.

公开(公告)号：US11804527B2

公开(公告)日：2023-10-31

申请号：US17376026

申请日：2021-07-14

Applicant: NXP USA, Inc.

Inventor： Vikas Shilimkar ,  Kevin Kim ,  Daniel Joseph Lamey ,  Bruce McRae Green ,  Ibrahim Khalil ,  Humayun Kabir

IPC: H01L29/417 ,  H01L29/778 ,  H01L23/00 ,  H01L29/40 ,  H01L23/48

CPC classification number: H01L29/41775 ,  H01L23/481 ,  H01L24/05 ,  H01L29/401 ,  H01L29/7786 ,  H01L2224/04042

Abstract: A transistor includes a source contact connected to a Through-Silicon Via (TSV). A drain contact is connected to a first pad. A gate structure is interposed between the source contact and the drain contact. A second pad is connected to the gate structure, the second pad comprising a first side diametrically opposed to a second side, and a third side interposed therebetween, the source contact proximal to the third side, a first portion of the first side and a second portion of the second side.

公开(公告)号：US12237257B2

公开(公告)日：2025-02-25

申请号：US17448709

申请日：2021-09-24

Applicant: NXP USA, Inc.

Inventor： Vikas Shilimkar ,  Kevin Kim ,  Charles John Lessard ,  Humayun Kabir

IPC: H01L23/52 ,  H01L23/522 ,  H01L23/528

Abstract: A transistor includes a semiconductor substrate having a first terminal and a second terminal. An interconnect structure is formed on an upper surface of the semiconductor substrate, the interconnect structure being formed of multiple layers of dielectric material and electrically conductive material. The electrically conductive material of the interconnect structure includes a pillar in electrical contact with the first terminal, a first runner electrically connected to the pillar, a tap interconnect in electrical contact with the second terminal, a second runner electrically connected to the tap interconnect, a shield structure positioned between the pillar and the tap interconnect, and a shield runner electrically connected to the shield structure, the shield runner overlying the second runner in a direction perpendicular to the upper surface of the semiconductor substrate.

公开(公告)号：US20220013451A1

公开(公告)日：2022-01-13

申请号：US17448709

申请日：2021-09-24

Applicant: NXP USA, Inc.

Inventor： Vikas Shilimkar ,  Kevin Kim ,  Charles John Lessard ,  Humayun Kabir

IPC: H01L23/522 ,  H01L23/528

Abstract: A transistor includes a semiconductor substrate having a first terminal and a second terminal. An interconnect structure is formed on an upper surface of the semiconductor substrate, the interconnect structure being formed of multiple layers of dielectric material and electrically conductive material. The electrically conductive material of the interconnect structure includes a pillar in electrical contact with the first terminal, a first runner electrically connected to the pillar, a tap interconnect in electrical contact with the second terminal, a second runner electrically connected to the tap interconnect, a shield structure positioned between the pillar and the tap interconnect, and a shield runner electrically connected to the shield structure, the shield runner overlying the second runner in a direction perpendicular to the upper surface of the semiconductor substrate.