公开(公告)号：US5440733A

公开(公告)日：1995-08-08

申请号：US98076

申请日：1993-07-28

申请人： Tetsuya Yamazaki ,  Kousuke Takahashi

发明人： Tetsuya Yamazaki ,  Kousuke Takahashi

IPC分类号： G06F17/30 ,  H04L29/06 ,  G06F15/00 ,  G06F7/04

CPC分类号： H04L29/06 ,  Y10S707/99945

摘要： In a token train retrieval device including a memory device (24) for memorizing a plurality of tokens each of which starts at a starting address and ends at an end address and each of which has a nest level selected from a plurality of nest levels and comprises a header and a data set where header comprises a data length code and a data identifier code including a nest bit, a retrieval condition memory (25) memorizes a retrieval condition including a plurality of designated nest level codes and a plurality of designated identifier codes. A header register (26) holds the data length code, the data identifier code, and the nest bit as a held data length code, a held data identifier code, and a held nest bit. Responsive to the held data length code, a supplied header, and a decided nest level code, a checking circuit (27) produces a matching signal when the retrieval condition is satisfied. An intra-train address generating circuit (29) generates an intra-train address variable in accordance with the matching signal and the held data length code. Supplied with the intra-train address and the held data length code, an end address calculating circuit (30) calculates the end address of each token as a calculated address. Responsive to the intra-train address, the calculated address, and the held nest bit, a nest level decision circuit (31) supplies the checking circuit with the decided nest level code indicative of one of the nest levels.

摘要翻译： 在令牌列车检索装置中，包括用于存储多个令牌的存储器件（24），每个令牌以起始地址开始并在结束地址结束，并且每个令牌具有从多个嵌套级别中选择的嵌套级别，并且包括 标题和数据组，其中报头包括数据长度代码和包括嵌套位的数据标识符代码，检索条件存储器（25）存储包括多个指定的嵌套级代码和多个指定标识符代码的检索条件。 标头寄存器（26）将数据长度代码，数据标识符代码和嵌套位保存为保持的数据长度代码，保持的数据标识符代码和保持的嵌套位。 响应于所保持的数据长度代码，提供的标题和确定的嵌套级代码，检查电路（27）在满足检索条件时产生匹配信号。 列车内地址生成电路（29）根据匹配信号和保持的数据长度码生成列车内地址变量。 提供列车内地址和持有的数据长度代码，结束地址计算电路（30）计算每个令牌的结束地址作为计算的地址。 嵌套级决定电路（31）响应于列车内地址，计算出的地址和所保持的嵌套位，向检查电路提供指示嵌套级别之一的所确定的嵌套级代码。

公开(公告)号：US5210827A

公开(公告)日：1993-05-11

申请号：US621715

申请日：1990-12-05

申请人： Kousuke Takahashi ,  Tetsuya Yamazaki

发明人： Kousuke Takahashi ,  Tetsuya Yamazaki

IPC分类号： H04L29/06 ,  G06F13/38

CPC分类号： G06F13/387

摘要： When a nest level judging device is supplied with tokens each of which has a nest level selected from first through N-th nest levels as a selected level and each of which comprises a header and a data set where the header comprises a data length code and a data identifier code including a nest bit, a counter (31) produces an address signal for specifying starting and end addresses of each of the tokens and a varying address varying from the starting address to the end address. Supplied with the header, a header register (32) produces a data length signal representative of the data length code and a nest bit signal which represents that the each of the tokens is nested in the data set thereof. Supplied with the address signal and the data length signal, an end address calculator (33) calculates the end address of the respective tokens and produces an end address signal representative of the end address. Responsive to selection signals, a selector (34) delivers the end addresses of the respective tokens as first through N-th end addresses. Supplied with the nest bit signal, the address signal, and the first through the N-th end addresses, a decision unit (35) decides a decided nest level, indicative of one of the first through the N-th nest levels that is selected as the selected level. The level decision unit delivers the decided nest level as one of the selection signals to the selector.

公开(公告)号：US5208656A

公开(公告)日：1993-05-04

申请号：US674605

申请日：1991-03-25

申请人： Haruhiko Matsuyama ,  Mitsuo Yoshimoto ,  Jun Tanaka ,  Fusaji Shoji ,  Hitoshi Yokono ,  Takashi Inoue ,  Tetsuya Yamazaki ,  Minoru Tanaka ,  Hidetaka Shigi

发明人： Haruhiko Matsuyama ,  Mitsuo Yoshimoto ,  Jun Tanaka ,  Fusaji Shoji ,  Hitoshi Yokono ,  Takashi Inoue ,  Tetsuya Yamazaki ,  Minoru Tanaka ,  Hidetaka Shigi

IPC分类号： H05K3/46 ,  H01L21/60 ,  H01L23/498

CPC分类号： H01L23/49827 ,  H01L23/49822 ,  H01L2924/0002 ,  H01L2924/09701

摘要： A multilayer wiring substrate having high reliability can be produced in good productivity by subjecting metal wiring layers to stabilization treatment on the surface with a metal such as Cr, Mo or the like or an aqueous solution of water glass so as to prevent generation of hillocks or whiskers and to improve chemical resistance.

摘要翻译： 通过使金属布线层通过金属如Cr，Mo等在表面上进行稳定化处理或水玻璃水溶液，可以以良好的生产率制造具有高可靠性的多层布线基板，以防止产生小丘或 晶须并改善耐化学性。