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公开(公告)号:US11940938B2
公开(公告)日:2024-03-26
申请号:US17855907
申请日:2022-07-01
申请人: Dell Products, L.P.
发明人: Matthew H. Fredette
CPC分类号: G06F13/387 , G06F9/45545 , G06F9/45558 , G06F13/4027 , G06F2009/45579
摘要: A hypervisor is configured to bridge I/O operations between the NVMeoPCIe version of the NVMe I/O protocol and the NVMeoF version of the NVMe I/O protocol. By providing a bridging hypervisor, guests can use the NVMePCIe version of the NVMe I/O protocol for storage access operations, while the hypervisor can use the NVMeoF version of the NVMe I/O protocol to implement the storage access operations on attached storage resources of the storage system. The hypervisor handles administrative actions associated with creating, managing, and destroying submission queues and completion queues. Once the desired queue configuration has been created, NVMeoPCIe I/O operations are able to be transparently bridged by the hypervisor, which greatly reduces the amount of processing that would be required if the hypervisor were required to terminate each NVMeoPCIe I/O operation, generate corresponding NVMeoF I/O operations, and keep track of each such pair of I/O operations.
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公开(公告)号:US20240095204A1
公开(公告)日:2024-03-21
申请号:US18262107
申请日:2021-01-28
CPC分类号: G06F13/387 , G06F13/102
摘要: In one example in accordance with the present disclosure, a computing device is described. The computing device includes a configurable logic element. The configurable logic element 1) connects to a number of peripheral electronic devices, with at least one peripheral electronic device having a different native protocol relative to another peripheral electronic device and 2) prepares and packages a number of signals to be transmitted across a uniform transmission protocol. The computing device also includes a communication pathway to transmit packaged signals to a driver using the uniform transmission protocol. The computing device also includes the driver to 1) unpack the number of signals from the aggregated data transmission and 2) represents the number of peripheral electronic devices to an operating system of the computing device.
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公开(公告)号:US20240028542A1
公开(公告)日:2024-01-25
申请号:US18478827
申请日:2023-09-29
发明人: Mohsen Nahvi
IPC分类号: G06F13/38
CPC分类号: G06F13/385 , G06F13/387 , G06F2213/0042
摘要: In some embodiments, a system for communicating USB information via a non-USB extension medium is provided. The system comprises a downstream facing port device (DFP device). The DFP device is configured to receive, via the non-USB extension medium, an ACK IN packet addressed to a first endpoint while receiving DATA packets from a second endpoint. The DFP device is further configured to detect an end of transmission of the DATA packets from the second endpoint; determine a number of packets that can be received from the first endpoint during a remaining amount of time in a current bus interval; and transmit at least one synthetic ACK IN packet to the first endpoint based on the number of packets.
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公开(公告)号:US11882060B2
公开(公告)日:2024-01-23
申请号:US18058015
申请日:2022-11-22
发明人: Riaz Khan , Atri Indiresan , Manas Pati
CPC分类号: H04L49/557 , G06F13/387 , H04L49/15 , H04L49/70 , H04L67/1095 , H04L69/08
摘要: An embodiment is directed to switchover operations with a mobile virtualized network device in a mobile device. The mobile virtualized hardware switchover operations may be used to selectively and temporarily provide virtualized control-plane operations to the data-plane of a non-redundant network device undergoing an upgrade or a reboot of its control plane. A non-redundant network device may operate hitless, or near hitless, operation even when its control plane is unavailable.
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公开(公告)号:US20240004820A1
公开(公告)日:2024-01-04
申请号:US17855907
申请日:2022-07-01
申请人: Dell Products, L.P.
发明人: Matthew H. Fredette
CPC分类号: G06F13/387 , G06F13/4027 , G06F2009/45579 , G06F9/45545 , G06F9/45558
摘要: A hypervisor is configured to bridge I/O operations between the NVMeoPCIe version of the NVMe I/O protocol and the NVMeoF version of the NVMe I/O protocol. By providing a bridging hypervisor, guests can use the NVMePCIe version of the NVMe I/O protocol for storage access operations, while the hypervisor can use the NVMeoF version of the NVMe I/O protocol to implement the storage access operations on attached storage resources of the storage system. The hypervisor handles administrative actions associated with creating, managing, and destroying submission queues and completion queues. Once the desired queue configuration has been created, NVMeoPCIe I/O operations are able to be transparently bridged by the hypervisor, which greatly reduces the amount of processing that would be required if the hypervisor were required to terminate each NVMeoPCIe I/O operation, generate corresponding NVMeoF I/O operations, and keep track of each such pair of I/O operations.
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公开(公告)号:US11789882B2
公开(公告)日:2023-10-17
申请号:US17544585
申请日:2021-12-07
发明人: Zixiang Wang
CPC分类号: G06F13/387 , G06F13/102
摘要: A sensor configuration method, an apparatus, computer equipment and a storage medium are disclosed. The method includes acquiring connection configuration information generated based on user input, querying for a target sensor driver matched with a target sensor represented by the sensor identifier in a device driver set, calling a target communication port driver matched with the target communication port represented by the communication port identifier and establishing communications with the target sensor by the target sensor driver and the target communication port driver. The connection configuration information includes a sensor identifier and a communication port identifier. The device driver set is pre-stored with a number of sensor drivers corresponding to a number of sensors.
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公开(公告)号:US11775468B2
公开(公告)日:2023-10-03
申请号:US17060204
申请日:2020-10-01
发明人: Klaus Wessling
IPC分类号: G06F13/42 , G06F13/38 , G06F9/4401 , G06F13/40
CPC分类号: G06F13/4221 , G06F9/4401 , G06F13/387 , G06F13/409 , G06F13/4068
摘要: A method for transmitting data between a peripheral device and a data acquisition unit, the data acquisition unit having a configurable communication interface via which the data are transmitted according to one of a number of defined communication protocols, includes: carrying out a communication protocol analysis by the peripheral device upon connection to a power supply; and carrying out an adaptation of the configurable communication interface of the peripheral device after detection of a communication protocol, providing a detected communication protocol, used by the data acquisition unit in order to carry out data exchange according to the detected communication protocol.
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公开(公告)号:US11749318B2
公开(公告)日:2023-09-05
申请号:US17888457
申请日:2022-08-15
发明人: Richard C. Murphy , Glen E. Hush , Honglin Sun
CPC分类号: G11C7/1045 , G06F9/30189 , G06F9/30196 , G06F9/546 , G06F13/387 , G11C7/1039
摘要: Apparatuses and methods can be related to configuring interface protocols for memory. An interface protocol can define the commands received by a memory device utilizing pins of an interface of a memory device. An interface protocol used by a memory device can be implemented utilizing a decoder of signals provided through the pins of the memory device. The decoder utilized by a memory device can be selected by setting a mode register of the memory device.
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公开(公告)号:US20190220433A1
公开(公告)日:2019-07-18
申请号:US16378984
申请日:2019-04-09
发明人: Yutaka Kawai , Yohichi Miwa
CPC分类号: G06F13/387 , G06F7/5057 , G06F9/223 , G06F13/124 , G06F15/7867 , G06F15/7892 , G06F2213/0026
摘要: A programmable apparatus for executing a function is disclosed. The programmable apparatus includes a physical interface configured to be connected with an external apparatus. The programmable apparatus also includes a function logic circuit configured to execute the function on the programmable apparatus. The programmable apparatus further includes a plurality of peripheral logic circuits, each of which is configured to connect the function logic circuit with the physical interface using a respective protocol. The programmable apparatus also includes a selector circuit configured to select one from among the plurality of the peripheral logic circuits to activate.
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公开(公告)号:US20190163659A1
公开(公告)日:2019-05-30
申请号:US15822703
申请日:2017-11-27
发明人: Ellis A. PINDER , Juan J. GIOL , Matthew E. SIMMS
CPC分类号: G06F13/387 , G06F13/385 , G06F13/4022 , G06F13/4265 , G06F21/575 , G06F21/79 , G06F2213/3852 , G06K7/0021 , G06K19/07732
摘要: A secure digital format card that includes two interfaces to a processor is provided, comprising a housing, and a processor that includes a secure digital input/output (SDIO) interface, a second interface, and further connections different from the interfaces. A first set and second set of pads are located at the housing, a subset of the first set for communicating with the processor via the SDIO interface. A subset of the second set for communicating with the processor via the second interface, and a further subset of the second set for communicating with the processor via the further connections. The processor is configured to: enable the subset of the second set of pads via the second interface when enable data is received via the one or more further connections, from the further subset of the second set of pads.
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