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    Event scheduler for an electrical circuit design to account for hold time violations
    22.
    发明授权
    Event scheduler for an electrical circuit design to account for hold time violations 有权
    用于电路设计的事件调度器来解决持续时间违规

    公开(公告)号：US08473887B2

    公开(公告)日：2013-06-25

    申请号：US13049489

    申请日：2011-03-16

    申请人： Tong Xiao

    发明人： Tong Xiao

    IPC分类号： G06F17/50

    CPC分类号： G06F17/504 ,  G06F2217/62 ,  G06F2217/84

    摘要： Implementations of the present disclosure involve an apparatus and/or method for identifying and classify nodes of an electrical circuit design to account for hold time violations occurring within the circuit. The nodes may be ordered based on a criticality of the nodes that may aid in identifying those nodes of the circuit where hold time violations may be corrected. In one embodiment, the criticality may relate to the number of potentially violating paths that utilize the identified nodes such that corrective measures applied at those nodes may correct several hold time violating paths. In addition, criticality may be scaled utilizing an available buffer library and other timing information. Thus, by utilizing the methods and/or apparatuses of the present disclosure, the locations where timing violation corrective measures may be applied that improve or correct several violating data paths at once may be identified in such a manner so as to reduce the number of overall corrections made to the circuit design, reducing the cost and necessary time associated with the corrections.

    摘要翻译： 本公开的实现涉及用于识别和分类电路设计的节点以解决在电路内发生的保持时间违反的装置和/或方法。 可以基于节点的关键性来排序节点，这些节点可能有助于识别电路的那些节点，其中可以校正保持时间违规。 在一个实施例中，关键性可以涉及利用所识别的节点的潜在违反路径的数量，使得在那些节点处应用的校正措施可以纠正多个保持时间违反路径。 此外，可以使用可用的缓冲库和其他定时信息来缩放关键性。 因此，通过利用本公开的方法和/或装置，可以以这样的方式识别可以一次改进或校正若干违反数据路径的定时违规纠正措施的位置，以便减少整体的数量 对电路设计进行了更正，降低了与修正相关的成本和必要的时间。