摘要:
A mobile user interface suitable for mobile computing devices uses device position/orientation in real space to select a portion of content that is displayed. Content (e.g., documents, files or a desktop) is presumed fixed in virtual space with the mobile user interface displaying a portion of the content as if viewed through a camera or magnifying glass. Data from motion, distance or position sensors are used to determine the relative position/orientation of the device with respect to the content to select the portion for display. Content elements can be selected by centering the display on the desired portion, obviating the need for cursors and pointing devices (e.g., mouse or touchscreen). Magnification can be manipulated by moving the device away from or towards the user. 3-D content viewing may be enabled by sensing the device orientation and displaying content that is above or below the display in 3-D virtual space.
摘要:
A device is described that includes an encoder/decoder (CODEC) in which functionality is partitioned between a video front end (VFE) and a video back end (VBE). The VFE encapsulates functionality and image processing operations to support a variety of applications, and presents a flexible inter-processor by which an external master device can easily control these operations. The video back end (VBE) operates as an encoder and/or a decoder to generate encoded and/or decoded video sequences. The VFE and VBE may execute within an operating environment provided by a slave device.
摘要:
This disclosure describes video encoding techniques capable of reducing the number of processing cycles and memory transfers necessary to encode a video sequence. In this manner, the disclosed video encoding techniques may increase video encoding speed and reduce power consumption. In general, the video encoding techniques make use of a candidate memory that stores video blocks in columns corresponding to a search space for a motion estimation routine. A memory control unit addresses the candidate memory to retrieve multiple pixels in parallel for simultaneous comparison to pixels in a video block to be encoded, e.g., using Sum of Absolute Difference (SAD) or Sum of Squared Difference (SSD) techniques. A difference processor performs the parallel calculations. In addition, for subsequent video blocks to be encoded, the candidate memory can be incrementally updated by loading a new column of video blocks, rather than reloading the entire search space.
摘要:
A voice recognition system applies speaker-dependent modification functions to acoustic feature vectors prior to voice recognition pattern matching against a speaker-independent acoustic model. An adaptation engine matches a set of acoustic feature vectors X with an adaptation model to select a speaker-dependent feature vector modification function f( ), which is then applied to X to form a modified set of acoustic feature vectors f(X). Voice recognition is then performed by correlating the modified acoustic feature vectors f(X) with a speaker-independent acoustic model.
摘要:
A voice recognition system is disclosed wherein a feature extraction apparatus is located in a remote station. The feature extraction apparatus extracts features from an input speech frame and then provides the extracted features to a central processing station. In the central processing station, the features are provided to a word decoder which determines the syntax of the input speech frame.
摘要:
A voice recognition system having a feature extraction apparatus is located in a remote station. The feature extraction apparatus extracts features from an input speech frame and then provides the extracted features to a central processing station. In the central processing station, the features are provided to a word decoder which determines the syntax of the input speech frame.
摘要:
A device is described that includes an encoder/decoder (CODEC) in which functionality is partitioned between a video front end (VFE) and a video back end (VBE). The VFE encapsulates functionality and image processing operations to support a variety of applications, and presents a flexible inter-processor by which an external master device can easily control these operations. The video back end (VBE) operates as an encoder and/or a decoder to generate encoded and/or decoded video sequences. The VFE and VBE may execute within an operating environment provided by a slave device.
摘要:
This disclosure is directed to encoding techniques that can be used to improve encoding of digital video data. The techniques can be implemented by an encoder of a digital video device in order to reduce the number of computations and possibly reduce power consumption during video encoding. More specifically, video encoding techniques are described which utilize one or more programmable thresholds in order to terminate the execution of various computations when the computations would be unlikely to improve the encoding. By terminating computations prematurely, the amount of processing required for video encoding can be reduced, and power can be conserved.
摘要:
This disclosure is directed to encoding techniques that can be used to improve encoding of digital video data. The techniques can be implemented by an encoder of a digital video device in order to reduce the number of computations and possibly reduce power consumption during video encoding. More specifically, video encoding techniques are described which utilize one or more programmable thresholds in order to terminate the execution of various computations when the computations would be unlikely to improve the encoding. By terminating computations prematurely, the amount of processing required for video encoding can be reduced, and power can be conserved.
摘要:
A method and apparatus for implementing a vocoder in a application specific integrated circuit (ASIC) is provided. The apparatus contains a DSP core that performs computations in accordance with a reduced instruction set (RISC) architecture. The circuit further includes a specifically designed slave processor to the DSP core referred to as the minimization processor. The apparatus further comprises a specifically designed block normalization circuitry.