公开(公告)号：US5784532A

公开(公告)日：1998-07-21

申请号：US197417

申请日：1994-02-16

申请人： John G. McDonough ,  Chienchung Chang ,  Randeep Singh ,  Charles E. Sakamaki ,  Ming-Chang Tsai ,  Prashant Kantak

发明人： John G. McDonough ,  Chienchung Chang ,  Randeep Singh ,  Charles E. Sakamaki ,  Ming-Chang Tsai ,  Prashant Kantak

IPC分类号： G10L19/08 ,  G06F5/01 ,  G10L19/00 ,  G10L19/04 ,  G10L19/06 ,  G10L19/12 ,  G10L19/14 ,  H03M7/30 ,  G10L9/00

CPC分类号： G06F5/01 ,  G10L19/07 ,  G10L19/16

摘要： A method and apparatus for implementing a vocoder in a application specific integrated circuit (ASIC) is provided. The apparatus contains a DSP core that performs computations in accordance with a reduced instruction set (RISC) architecture. The circuit further includes a specifically designed slave processor to the DSP core referred to as the minimization processor. The apparatus further comprises a specifically designed block normalization circuitry.

摘要翻译： 提供了一种在专用集成电路（ASIC）中实现声码器的方法和装置。 该装置包含根据简化指令集（RISC）架构执行计算的DSP内核。 该电路还包括被称为最小化处理器的被专门设计的到DSP核的从属处理器。 该装置还包括专门设计的块归一化电路。

公开(公告)号：US5727123A

公开(公告)日：1998-03-10

申请号：US575303

申请日：1995-12-20

申请人： John G. McDonough ,  Chienchung Chang ,  Randeep Singh ,  Charles E. Sakamaki ,  Ming-Chang Tsai ,  Prashant Kantak

发明人： John G. McDonough ,  Chienchung Chang ,  Randeep Singh ,  Charles E. Sakamaki ,  Ming-Chang Tsai ,  Prashant Kantak

IPC分类号： G10L19/08 ,  G06F5/01 ,  G10L19/00 ,  G10L19/04 ,  G10L19/06 ,  G10L19/12 ,  G10L19/14 ,  H03M7/30 ,  G10L3/00

CPC分类号： G06F5/01 ,  G10L19/07 ,  G10L19/16

摘要： A method and apparatus for implementing a vocoder in a application specific integrated circuit (ASIC) is provided. The apparatus contains a DSP core that performs computations in accordance with a reduced instruction set (RISC) architecture. The circuit further includes a specifically designed slave processor to the DSP core referred to as the minimization processor. The apparatus further comprises a specifically designed block normalization circuitry.

摘要翻译： 提供了一种在专用集成电路（ASIC）中实现声码器的方法和装置。 该装置包含根据简化指令集（RISC）架构执行计算的DSP内核。 该电路还包括被称为最小化处理器的被专门设计的到DSP核的从属处理器。 该装置还包括专门设计的块归一化电路。

公开(公告)号：US07298777B2

公开(公告)日：2007-11-20

申请号：US10455020

申请日：2003-06-06

申请人： John G. McDonough ,  Gibong Jeong ,  Karim Abdulla ,  Rajiv R. Nambiar ,  William S. Clark, Jr.

发明人： John G. McDonough ,  Gibong Jeong ,  Karim Abdulla ,  Rajiv R. Nambiar ,  William S. Clark, Jr.

IPC分类号： H04B1/00

CPC分类号： H04B1/708

摘要： This disclosure is generally directed to communication systems, devices used in communication systems and associated methods which may implement parallel hypothesis search techniques. The disclosed parallel hypothesis search techniques may permit a hypothesis to be dismissed early (i.e., before hypotheses in other searchers have completed their evaluation). Early hypothesis dismissal permits a new hypothesis to be loaded into the searcher while other searchers advantageously continue to evaluate their hypotheses.

摘要翻译： 本公开通常涉及通信系统，在通信系统中使用的设备和可以实现并行假设搜索技术的相关方法。 公开的平行假设检索技术可以允许早期解除假设（即，在其他搜索者的假设已经完成其评估之前）。 早期假设解雇允许将新假设加载到搜索者中，而其他搜索者有利地继续评估其假设。

公开(公告)号：US06559714B2

公开(公告)日：2003-05-06

申请号：US09820050

申请日：2001-03-28

申请人： Edwin Park ,  John G. McDonough

发明人： Edwin Park ,  John G. McDonough

IPC分类号： H03K500

CPC分类号： H03H1/02

摘要： A signal filter employs digital control signals to selectively establish and adjust analog impedance components of the filter. In the case of a first-order R-C filter, adjustable resistance and reactance assemblies are coupled in series. The resistance assembly has multiple parallel signal paths sharing a common input and output. Each signal path includes a prescribed electrical resistance and a digital switch to selectively enable and disable the resistance. Between the common input and output, the signal paths provide a collective resistance which varies depending upon which switches have been activated. The reactance assembly is similar to the resistance assembly, with capacitors or inductors instead of resistors. A digital controller selectively activates the switches to adjust the assemblies' respective resistance and reactance.

公开(公告)号：US06452959B1

公开(公告)日：2002-09-17

申请号：US09322373

申请日：1999-05-28

申请人： John G. McDonough

发明人： John G. McDonough

IPC分类号： H04B169

CPC分类号： H04J13/0022 ,  H04B1/707 ,  H04J13/10

摘要： A method of generating one or more pseudorandom noise (PN) sequences for use in spread spectrum communications includes the steps of providing data at an input of memory which stores bits associated with a pseudorandom noise (PN) sequence: changing the data; and for each of a plurality of changes of the data, providing a selected PN bit of the PN sequence at an output of the memory based on the data.

摘要翻译： 一种产生用于扩展频谱通信的一个或多个伪随机噪声（PN）序列的方法包括以下步骤：在存储与伪随机噪声（PN）序列相关联的位的存储器的输入端提供数据：改变数据; 并且对于数据的多个改变中的每一个，基于该数据在存储器的输出处提供PN序列的选择的PN位。

公开(公告)号：US07403507B2

公开(公告)日：2008-07-22

申请号：US09883740

申请日：2001-06-18

申请人： John G. McDonough ,  Juncheng C. Liu ,  Yan Hui ,  Chunhao Chen

发明人： John G. McDonough ,  Juncheng C. Liu ,  Yan Hui ,  Chunhao Chen

IPC分类号： H04B7/216

CPC分类号： H04B1/70756 ,  H04B2201/70709

摘要： A sleep control system and method are provided that permit a reference clock and the direct sequence spread spectrum (DSSS) modem in a mobile station receiver to be turned off and turned back on at arbitrary points in time while still maintaining accurate base station system time. Accurate timing is made possible through a number of techniques including precise initial calibration using a rising edge/falling edge averaging system, determining the sleep clock and reference clock frequencies, and the determination of the frequency drift of the sleep clock that occurred during the previous sleep interval.

摘要翻译： 提供一种睡眠控制系统和方法，其允许移动台接收机中的参考时钟和直接序列扩频（DSSS）调制解调器在任意时间点被关闭并重新接通，同时仍保持精确的基站系统时间。 通过包括使用上升沿/下降沿平均系统的精确初始校准，确定睡眠时钟和参考时钟频率以及确定在先前睡眠期间发生的睡眠时钟的频率漂移的许多技术，可以实现准确的定时 间隔。

公开(公告)号：US07295598B2

公开(公告)日：2007-11-13

申请号：US10439400

申请日：2003-05-16

申请人： John G. McDonough ,  Gibong Jeong ,  Karim Abdulla ,  Rajiv R. Nambiar ,  William S. Clark, Jr.

发明人： John G. McDonough ,  Gibong Jeong ,  Karim Abdulla ,  Rajiv R. Nambiar ,  William S. Clark, Jr.

IPC分类号： H04B1/00

CPC分类号： H04B1/70755

摘要： A method and system for processing the results of searches for signals in a direct sequence spread spectrum communications system in an intelligent and efficient manner. A preferred embodiment comprises a search engine (for example, search engine 405) and a hardware result processor (for example, result processor 410) with a memory (for example, memory 415) as an interface. The search engine may perform multiple correlations of a pilot channel and then writes the correlation results exceeding a specified threshold to the memory. The result processor reads the correlation results from the memory and performs result filtering and builds a list of maximum value correlation results. The result processor and the search engine functions with independence from one another therefore, there is therefore, little wasted overhead where one has to wait for the other. The result filtering also makes it simpler to combine signal multipaths and simplifies pilot channel strength comparisons.

摘要翻译： 一种用于以智能且有效的方式处理在直接序列扩频通信系统中搜索信号的结果的方法和系统。 优选实施例包括具有作为接口的存储器（例如，存储器415）的搜索引擎（例如，搜索引擎405）和硬件结果处理器（例如，结果处理器410）。 搜索引擎可以执行导频信道的多个相关性，然后将超过规定阈值的相关结果写入存储器。 结果处理器从存储器读取相关结果，并执行结果过滤，并建立最大值相关结果列表。 结果处理器和搜索引擎的功能彼此独立，因此，因此，必须等待另一个的开销很少。 结果滤波也使得组合信号多路径更简单，并简化了导频信道强度比较。

公开(公告)号：US07120186B2

公开(公告)日：2006-10-10

申请号：US09955534

申请日：2001-09-18

申请人： John G. McDonough

发明人： John G. McDonough

IPC分类号： H04B1/69

CPC分类号： H04J13/0029 ,  H04B2201/70707 ,  H04J13/10

摘要： Methods and apparatus for use in generating data sequences for direct sequence spread spectrum (DSSS) communications are described. One exemplary method includes the steps of serially generating a pseudo random noise (PN) sequence by, for each count value i of a plurality of count values, retrieving from memory a bit of the PN sequence corresponding to the (i)th position in the PN sequence. The exemplary method includes the further steps of serially generating a Gold code sequence by, for each count value i of the plurality of count values, retrieving from memory a bit of the PN sequence corresponding to the (i+n)th position in the PN sequence, retrieving from memory a bit of the PN sequence corresponding to the (q*i)th position in the PN sequence, and adding the bit corresponding to the (i+n)th position with the bit corresponding to the (q*i)th position.

公开(公告)号：US06987799B2

公开(公告)日：2006-01-17

申请号：US09848500

申请日：2001-05-03

申请人： John G. McDonough ,  Craig M. Julian

发明人： John G. McDonough ,  Craig M. Julian

IPC分类号： H04B1/69 ,  H04B7/216

CPC分类号： H04B1/7115 ,  H04B1/7117 ,  H04B1/712

摘要： A Direct Sequence Spread Spectrum (DSSS) receiver system (100) combines and orders the soft symbols from associated information channels. The system permits a QPSK channel to be demodulated as a pair of BPSK channels, and the soft symbols of the demodulated BPSK channels to be multiplexed into a single information channel. The receiver system (100) includes a plurality of demodulating fingers (102–106). Each demodulating finger accepts modulation parameters and a sample stream, while supplying soft symbols with indexing information so that information channels can be subsequently multiplexed into a single information channel. A method for ordering the soft symbols of associated information channels in a DSSS system is also provided.

摘要翻译： 直接序列扩频（DSSS）接收机系统（100）组合并对来自相关信息信道的软符号进行排序。 该系统允许QPSK信道被解调为一对BPSK信道，并且解调的BPSK信道的软符号被复用到单个信息信道中。 接收机系统（100）包括多个解调指（102-106）。 每个解调手指接受调制参数和采样流，同时向索引信息提供软符号，使得信息信道可以随后被多路复用到单个信息信道中。 还提供了一种用于在DSSS系统中排序关联信息信道的软符号的方法。

公开(公告)号：US5926786A

公开(公告)日：1999-07-20

申请号：US873000

申请日：1997-06-11

申请人： John G. McDonough ,  Way-Shing Lee

发明人： John G. McDonough ,  Way-Shing Lee

IPC分类号： G10L19/08 ,  G06F5/01 ,  G10L19/00 ,  G10L19/04 ,  G10L19/06 ,  G10L19/12 ,  G10L19/14 ,  H03M7/30 ,  G10L9/00

CPC分类号： G06F5/01 ,  G10L19/07 ,  G10L19/16

摘要： A method and apparatus for implementing a vocoder in a application specific integrated circuit (ASIC) is described. The apparatus contains a DSP core that performs computations in accordance with a reduced instruction set (RISC) architecture. The circuit further includes a specifically designed slave processor to the DSP core referred to as the minimization processor. The apparatus further includes a specifically designed block normalization circuitry.

摘要翻译： 描述了在专用集成电路（ASIC）中实现声码器的方法和装置。 该装置包含根据简化指令集（RISC）架构执行计算的DSP内核。 该电路还包括被称为最小化处理器的被专门设计的到DSP核的从属处理器。 该装置还包括专门设计的块归一化电路。