公开(公告)号：US20070180176A1

公开(公告)日：2007-08-02

申请号：US11344411

申请日：2006-01-31

申请人： Fong Pong ,  Lief O'Donnell

发明人： Fong Pong ,  Lief O'Donnell

IPC分类号： G06F13/00

CPC分类号： G06F12/0831 ,  G06F13/4045

摘要： A system includes a first bus segment and a second bus segment. The first bus segment is operatively coupled to one or more first bus agents, where the first bus agents are configured for writing messages to the first bus segment and reading messages from the first bus segment and the second bus segment, which is separate from the first bus segment, is operatively coupled to one or more second bus agents. The first bus agents are configured for writing messages to the first bus segment and reading messages from the first bus segment. The system also includes first electrical circuitry operably coupled to the first bus segment and the second bus segment and configured to read messages written on the first bus segment and to write the messages onto the second bus segment and second electrical circuitry operably coupled to the first bus segment and the second bus segment and configured to read messages written on the second bus segment and to write the messages onto the first bus segment.

摘要翻译： 系统包括第一总线段和第二总线段。 第一总线段可操作地耦合到一个或多个第一总线代理，其中第一总线代理被配置用于将消息写入第一总线段并从第一总线段和第二总线段读取消息，该第一总线段与第一总线段 总线段，可操作地耦合到一个或多个第二总线代理。 第一总线代理被配置为将消息写入第一总线段并从第一总线段读取消息。 该系统还包括可操作地耦合到第一总线段和第二总线段的第一电路，并且被配置为读取在第一总线段上写入的消息并且将消息写入第二总线段上，并将第二电路可操作地耦合到第一总线 段和第二总线段，并且被配置为读取写在第二总线段上的消息并将消息写入第一总线段。

公开(公告)号：US20060274787A1

公开(公告)日：2006-12-07

申请号：US11228362

申请日：2005-09-16

申请人： Fong Pong

发明人： Fong Pong

IPC分类号： H04L12/56 ,  H04J3/16 ,  H04L12/28 ,  H04J3/22

CPC分类号： G06F12/0875 ,  G06F12/1081 ,  G06F12/145 ,  H04L67/1097 ,  H04L69/12 ,  H04L69/16 ,  H04L69/161

摘要： Certain aspects of a method and system for an adaptive cache for memory protection table (MPT), memory translation table (MTT) and TCP context are provided. At least one of a plurality of on-chip cache banks integrated within a multifunction host bus adapter (MHBA) chip may be allocated for storing active connection context for any of a plurality of communication protocols. The MHBA chip may handle a plurality of protocols, such as an Ethernet protocol, a transmission control protocol (TCP), an Internet protocol (IP), Internet small computer system interface (iSCSI) protocol, and a remote direct memory access (RDMA) protocol. The active connection context may be stored within the allocated at least one of the plurality of on-chip cache banks integrated within the multifunction host bus adapter chip, based on a corresponding one of the plurality of communication protocols associated with the active connection context.

摘要翻译： 提供了用于存储器保护表（MPT），存储器转换表（MTT）和TCP上下文的自适应高速缓存的方法和系统的某些方面。 集成在多功能主机总线适配器（MHBA）芯片内的多个片上高速缓存组中的至少一个可以被分配用于存储用于多个通信协议中的任何一个的活动连接上下文。 MHBA芯片可以处理多个协议，诸如以太网协议，传输控制协议（TCP），因特网协议（IP），因特网小型计算机系统接口（iSCSI）协议和远程直接存储器访问（RDMA） 协议。 基于与主动连接上下文相关联的多个通信协议中的相应一个，活动连接上下文可以被存储在集成在多功能主机总线适配器芯片内的所分配的至少一个片上高速缓存存储器中。

公开(公告)号：US06728843B1

公开(公告)日：2004-04-27

申请号：US09451499

申请日：1999-11-30

申请人： Fong Pong ,  Tung Nguyen

发明人： Fong Pong ,  Tung Nguyen

IPC分类号： G06F1200

CPC分类号： G06F12/0828

摘要： A system and method for processing multiple main memory accesses in parallel includes transmitting from the processor to the system control unit a first and a second transaction. These transactions are decoded to determine their corresponding commands and addresses. The system control unit includes a qualifier and a scheduler that assigns each transaction to a particular finite state machine (FSM). Each FSM executes a single transaction until completed. Each FSM machine maintains a record or keeps track of the state of progress of a transaction that is being executed by the system control unit. The FSMs keep track of the data by storing the data, such as the current state of the transaction, the status of the data, and an identifier describing which processor issued the transaction, for each transaction in a data buffer. The data value corresponding to a particular transaction may be retrieved from the main memory using a FSM. Since a different FSM is used to retrieve data values, the execution of these transactions can be performed in parallel. Parallel processing of memory accesses using FSMs enhances the speed and efficiency of computer systems.

摘要翻译： 用于并行处理多个主存储器访问的系统和方法包括从处理器向系统控制单元发送第一和第二事务。 这些事务被解码以确定它们相应的命令和地址。 系统控制单元包括限定器和调度器，其将每个事务分配给特定的有限状态机（FSM）。 每个FSM执行一个事务直到完成。 每个FSM机器维护记录或跟踪系统控制单元正在执行的事务的进展状态。 FSM通过存储数据来跟踪数据，例如数据的当前状态，数据的状态以及描述哪个处理器发出交易的标识符，用于数据缓冲器中的每个事务。 可以使用FSM从主存储器检索对应于特定事务的数据值。 由于使用不同的FSM来检索数据值，因此可以并行执行这些事务。 使用FSM并行处理存储器访问可提高计算机系统的速度和效率。

公开(公告)号：US06490662B1

公开(公告)日：2002-12-03

申请号：US09561755

申请日：2000-04-29

申请人： Fong Pong ,  Tung Nguyen

发明人： Fong Pong ,  Tung Nguyen

IPC分类号： G06F1200

CPC分类号： G06F11/183 ,  G06F11/1666 ,  G06F11/18 ,  G06F12/0815

摘要： A computer system and method for enhancing the reliability of a computer system by combining a cache sync-flush engine with a replicated memory module includes placing a “lock” command on the common bus. The lock protects or controls accesses to a number of memory locations in the memory modules designated by the programmer. At any point in time, one processor can obtain the lock, and hence has access to the number of memory locations protected by the lock. Other processors may attempt to acquire or make a request for the same lock, however, the other processor will fail until the processor that has the lock has released (i.e., “unlocked”) the lock. The other processors will keep trying to get the lock. The processor that obtains the lock instructs the system control unit to begin logging or monitoring all subsequent memory addresses that appear on the common bus. After the processor gets the lock, it can start reading from and writing to the number of memory locations that are implemented as a number of replicated memory modules. A data value is then determined based on the data held by a majority of the replicated memory modules. The data value is transmitted to the cache of the processor. After the data is processed, an “unlock” command is transmitted from the processor to a system control unit that issues a write back request on the common bus that flushes the data value from the cache to the number of replicated memory modules.

摘要翻译： 通过将高速缓存同步冲洗引擎与复制的存储器模块组合来提高计算机系统的可靠性的计算机系统和方法包括在公共总线上放置“锁定”命令。 该锁保护或控制对由编程器指定的存储器模块中的多个存储器位置的访问。 在任何时间点，一个处理器可以获得锁定，因此可以访问被锁定保护的存储器位置的数量。 其他处理器可能尝试获取或请求相同的锁，但是，其他处理器将失败，直到具有锁的处理器已经释放（即，“解锁”）该锁。 其他处理器将继续尝试锁定。 获取锁的处理器指示系统控制单元开始记录或监视公共总线上出现的所有后续存储器地址。 处理器获得锁定后，它可以开始读取和写入实现为多个复制的内存模块的内存位置数。 然后基于大多数复制的存储器模块保存的数据来确定数据值。 数据值被发送到处理器的高速缓存。 在处理数据之后，从处理器向系统控制单元发送“解锁”命令，该系统控制单元在将数据值从高速缓存刷新到复制的存储器模块的数量的公共总线上发出回写请求。

公开(公告)号：US06449690B1

公开(公告)日：2002-09-10

申请号：US09344660

申请日：1999-06-25

申请人： Fong Pong ,  Gopalakrishnan Janakiraman

发明人： Fong Pong ,  Gopalakrishnan Janakiraman

IPC分类号： G06F1200

CPC分类号： G06F12/0893 ,  G06F12/084 ,  Y02D10/13

摘要： A caching method for using cache data stored in dynamic RAM embedded in a logic chip and cache tags stored in static RAM external to the logic chip. In general, there are at least two cache applications where this method can be employed. First, there are caches integral to a processor and interfaced to a processor pipeline. Second, there are caches external to a processor and interfaced with a shared bus.

摘要翻译： 一种缓存方法，用于使用存储在逻辑芯片中的动态RAM中存储的缓存数据，以及存储在逻辑芯片外部的静态RAM中的缓存标签。 通常，至少有两个缓存应用程序可以使用此方法。 首先，存在处理器集成的高速缓存，并与处理器管道连接。 第二，处理器外部存在高速缓存，并与共享总线接口。

公开(公告)号：US06360231B1

公开(公告)日：2002-03-19

申请号：US09258608

申请日：1999-02-26

申请人： Fong Pong ,  Lance Russell ,  Tung Nguyen

发明人： Fong Pong ,  Lance Russell ,  Tung Nguyen

IPC分类号： G06F1730

CPC分类号： G06F12/0815 ,  Y10S707/99952

摘要： A cache coherent distributed shared memory multi-processor computer system is provided which supports transactional memory semantics. A cache flushing engine and temporary buffer allow selective forced write-backs of dirty cache lines to the home memory. A flush can be performed from the updated cache to the temporary buffer and then to the home memory after confirmation of receipt or from the updated cache to the home memory directly with the temporary buffer holding the old data until confirmation that the home memory contains the update.

摘要翻译： 提供了一种支持事务性存储器语义的高速缓存一致分布式共享存储器多处理器计算机系统。 高速缓存刷新引擎和临时缓冲区允许有选择地将脏缓存行强制回写到家庭存储器。 可以在保存了旧数据的临时缓冲器之后，从更新的缓存到临时缓冲区执行刷新，然后在确认接收之后到家庭存储器或从更新的高速缓存直接到家庭存储器，直到确认家庭存储器包含更新 。

公开(公告)号：US6128702A

公开(公告)日：2000-10-03

申请号：US227133

申请日：1999-01-08

申请人： Ashley Saulsbury ,  Andreas Nowatzyk ,  Fong Pong

发明人： Ashley Saulsbury ,  Andreas Nowatzyk ,  Fong Pong

IPC分类号： G06F12/08 ,  G06F12/12

CPC分类号： G06F12/0897

摘要： An integrated processor/memory device comprising a main memory, a CPU, a victim cache, and a primary cache. The main memory comprises main memory banks. The victim cache stores victim cache sub-lines of words. Each of the victim cache sub-lines has a corresponding memory location in the main memory. When the CPU issues an address in the address space of the main memory, the victim cache determines whether a victim cache hit or miss has occurred in the victim cache. And, when a victim cache miss occurs, the victim cache replaces a selected victim cache sub-line of the victim cache sub-lines in the victim cache with a new victim cache sub-line. The primary cache comprises primary cache banks. Each of the primary cache banks stores one or more cache lines of words. Each cache line has a corresponding memory location in the corresponding main memory bank. When the CPU issues an address in the portion of the address space of the corresponding main memory bank, the corresponding primary cache bank determines whether a cache hit or a cache miss has occurred. When a cache miss occurs, the primary cache bank replaces a victim cache line of the cache lines in the primary cache bank with a new cache line from the corresponding memory location in the corresponding main memory bank specified by the issued address and routs a sub-line of the victim cache line as the new victim cache sub-line.

摘要翻译： 包括主存储器，CPU，受害缓存和主缓存的集成处理器/存储器设备。 主存储器包括主存储器。 受害者缓存存储受害者缓存子行的字。 每个受害者缓存子行在主存储器中具有对应的存储器位置。 当CPU在主存储器的地址空间中发出地址时，受害者缓存器确定受害者缓存中是否发生了受害者缓存命中或未命中。 而且，当发生受害者缓存未命中时，受害者缓存用新的受害者缓存子行替代受害者缓存中的受害者缓存子行的选定的受害者缓存子行。 主缓存包括主缓存组。 每个主缓存组存储一个或多个字的高速缓存行。 每个高速缓存行在相应的主存储体中具有对应的存储器位置。 当CPU在对应的主存储体的地址空间的部分中发出地址时，相应的主缓存组确定是否发生了高速缓存命中或高速缓存未命中。 当发生高速缓存未命中时，主缓冲存储体组使用来自由发布的地址指定的相应主存储器库中的对应存储器位置的新的高速缓存行替换主缓存组中的高速缓存行的牺牲缓存行， 线路的受害者缓存行作为新的受害者缓存子行。

公开(公告)号：US5900011A

公开(公告)日：1999-05-04

申请号：US675272

申请日：1996-07-01

申请人： Ashley Saulsbury ,  Andreas Nowatzyk ,  Fong Pong

发明人： Ashley Saulsbury ,  Andreas Nowatzyk ,  Fong Pong

IPC分类号： G06F12/08 ,  G06F12/12 ,  G06F15/78

CPC分类号： G06F12/0897

摘要： An integrated processor/memory device comprising a main memory, a CPU, a victim cache, and a primary cache. The main memory comprises main memory banks. The victim cache stores victim cache sub-lines of words. Each of the victim cache sub-lines has a corresponding memory location in the main memory. When the CPU issues an address in the address space of the main memory, the victim cache determines whether a victim cache hit or miss has occurred in the victim cache. And, when a victim cache miss occurs, the victim cache replaces a selected victim cache sub-line of the victim cache sub-lines in the victim cache with a new victim cache sub-line. The primary cache comprises primary cache banks. Each of the primary cache banks stores one or more cache lines of words. Each cache line has a corresponding memory location in the corresponding main memory bank. When the CPU issues an address in the portion of the address space of the corresponding main memory bank, the corresponding primary cache bank determines whether a cache hit or a cache miss has occurred. When a cache miss occurs, the primary cache bank replaces a victim cache line of the cache lines in the primary cache bank with a new cache line from the corresponding memory location in the corresponding main memory bank specified by the issued address and routs a sub-line of the victim cache line as the new victim cache sub-line.

公开(公告)号：US20130262880A1

公开(公告)日：2013-10-03

申请号：US13434556

申请日：2012-03-29

申请人： Fong Pong ,  Eric Spada ,  Karen Schramm

发明人： Fong Pong ,  Eric Spada ,  Karen Schramm

IPC分类号： G06F12/14

CPC分类号： G06F12/1441 ,  G06F12/1408 ,  G06F21/72 ,  G06F21/79 ,  G06F2211/007

摘要： A memory access circuit and a corresponding method are provided. The memory access circuit includes a crypto block in communication with a memory that encrypts data of a data block on a block basis. The memory access circuit also includes a fault injection block configured to inject faults to the data in the data block. The memory access circuit further includes a data scrambler and an address scrambler. The data scrambler is configured to scramble data in the memory by shuffling data bits within the data block in a plurality of rounds and mash the shuffled data bits with random data. The address scrambler is configured to distribute the scrambled data across the memory. A memory system including the memory access circuit is also disclosed to implement the corresponding method.

摘要翻译： 提供存储器访问电路和相应的方法。 存储器访问电路包括与以块为基础对数据块的数据进行加密的存储器通信的密码块。 存储器访问电路还包括被配置为将错误注入数据块中的数据的故障注入块。 存储器访问电路还包括数据加扰器和地址扰频器。 数据加扰器被配置为通过在多个循环中混洗数据块内的数据位来对存储器中的数据进行加扰，并使用随机数据将混洗的数据位混合。 地址扰频器被配置为在整个存储器中分配加扰的数据。 还公开了包括存储器访问电路的存储器系统以实现相应的方法。

公开(公告)号：US20110268119A1

公开(公告)日：2011-11-03

申请号：US12771453

申请日：2010-04-30

申请人： Fong Pong ,  Kwong-Tak Chui ,  Chun Ning ,  Patrick Lau

发明人： Fong Pong ,  Kwong-Tak Chui ,  Chun Ning ,  Patrick Lau

IPC分类号： H04L12/56

CPC分类号： H04L47/624 ,  H04L29/06095 ,  H04L29/0653 ,  H04L45/74 ,  H04L47/12 ,  H04L47/30 ,  H04L47/32 ,  H04L47/6275 ,  H04L49/3009 ,  H04L49/309

摘要： A method to process a packet is described herein. The method comprises receiving a packet including a header and a payload. The header is parsed using a packet processor to determine type and priority of the packet. The header is then processed using a hardware acceleration block based on one or more of incoming bandwidth, priority and type of the packet. The custom hardware acceleration block generates header modification data that is sent to the packet processor. The header is modified using the packet processor, based on the header modification data, to generate a modified header. The modified header is appended to the payload and transmitted.

摘要翻译： 本文描述了处理分组的方法。 该方法包括接收包括报头和净荷的分组。 使用分组处理器解析报头以确定分组的类型和优先级。 然后使用基于分组的输入带宽，优先级和类型中的一个或多个的硬件加速块来处理报头。 定制硬件加速块产生发送到分组处理器的报头修改数据。 使用分组处理器，基于报头修改数据来修改报头，以生成修改的报头。 修改的报头附加到有效载荷并传输。