公开(公告)号：US20240031591A1

公开(公告)日：2024-01-25

申请号：US18478519

申请日：2023-09-29

Applicant: Panasonic Intellectual Property Corporation of America

Inventor： Takashi HASHIMOTO ,  Kiyofumi ABE ,  Tadamasa TOMA ,  Takahiro NISHI ,  Ryuichi KANOH

IPC: H04N19/51 ,  H04N19/433

CPC classification number: H04N19/51 ,  H04N19/433

Abstract: An encoding method is provided for encoding a picture to generate a coded stream. The encoding method includes: generating a first prediction image of a current block included in a current picture by referring to a first region included in a reference picture different from the current picture; operating a bi-directional optical flow process to generate a second prediction image based on the first prediction image by referring to a second region included in the first region; and encoding the current block based on the second prediction image.

公开(公告)号：US20220368935A1

公开(公告)日：2022-11-17

申请号：US17865659

申请日：2022-07-15

Applicant: Panasonic Intellectual Property Corporation of America

Inventor： Takashi HASHIMOTO ,  Takahiro NISHI ,  Tadamasa TOMA ,  Kiyofumi ABE ,  Ryuichi KANOH

IPC: H04N19/513 ,  H04N19/105 ,  H04N19/176

Abstract: A decoder that decodes a current block using a motion vector includes: a processor; and memory. Using the memory, the processor: derives a first candidate vector from one or more candidate vectors of one or more neighboring blocks that neighbor the current block; determines, in a first reference picture for the current block, a first adjacent region that includes a position indicated by the first candidate vector; calculates evaluation values of a plurality of candidate regions included in the first adjacent region; and determines a first motion vector of the current block, based on a first candidate region having a smallest evaluation value among the evaluation values. The first adjacent region is included in a first motion estimation region determined based on the position indicated by the first candidate vector.

公开(公告)号：US20220103859A1

公开(公告)日：2022-03-31

申请号：US17550210

申请日：2021-12-14

Applicant: Panasonic Intellectual Property Corporation of America

Inventor： Takashi HASHIMOTO ,  Kiyofumi ABE ,  Tadamasa TOMA ,  Takahiro NISHI ,  Ryuichi KANOH

IPC: H04N19/52 ,  H04N19/159 ,  H04N19/182

Abstract: An encoder includes: circuitry; and memory, in which using the memory, the circuitry, in affine motion compensation prediction in inter prediction for a current block, places a limit on a range within which motion estimation or motion compensation is performed, and performs the motion compensation for the current block.

公开(公告)号：US20220021876A1

公开(公告)日：2022-01-20

申请号：US17488640

申请日：2021-09-29

Applicant: Panasonic Intellectual Property Corporation of America

Inventor： Ryuichi KANOH ,  Tadamasa TOMA ,  Takahiro NISHI ,  Kiyofumi ABE ,  Takashi HASHIMOTO

IPC: H04N19/117 ,  H04N19/14 ,  H04N19/176 ,  H04N19/196

Abstract: An encoder includes processing circuitry and memory. Using the memory, the processing circuitry: encodes and reconstructs an image to generate a reconstructed image; determines, according to a characteristic of a block in the reconstructed image, an interpolation method for interpolating pixels located outside a referable region including the block; interpolates the pixels located outside the referable region, using the interpolation method determined; and applies a filter to the block using the pixels interpolated.

公开(公告)号：US20210127114A1

公开(公告)日：2021-04-29

申请号：US17141849

申请日：2021-01-05

Applicant: Panasonic Intellectual Property Corporation of America

Inventor： Kiyofumi ABE ,  Takahiro NISHI ,  Takashi HASHIMOTO ,  Tadamasa TOMA

IPC: H04N19/13 ,  H04N19/157 ,  H04N19/91 ,  H04N19/18

Abstract: An encoder includes memory and circuitry accessible to the memory. The circuitry accessible to the memory: switches whether or not to apply arithmetic encoding to a binary data string in which image information has been binarized; binarizes frequency transform coefficient information according to different binarization formats between when arithmetic encoding is applied to the binary data string and when arithmetic encoding is not applied to the binary data string; and binarizes a part or the entirety of prediction parameter information according to a binarization format which is common between when arithmetic encoding is applied to the binary data string and when arithmetic encoding is not applied to the binary data string.

公开(公告)号：US20210067799A1

公开(公告)日：2021-03-04

申请号：US17081267

申请日：2020-10-27

Applicant: Panasonic Intellectual Property Corporation of America

Inventor： Takashi HASHIMOTO ,  Kiyofumi ABE ,  Tadamasa TOMA ,  Takahiro NISHI ,  Ryuichi KANOH

IPC: H04N19/52 ,  H04N19/159 ,  H04N19/182

Abstract: An encoder includes: circuitry; and memory, in which using the memory, the circuitry, in affine motion compensation prediction in inter prediction for a current block, places a limit on a range within which motion estimation or motion compensation is performed, and performs the motion compensation for the current block.

公开(公告)号：US20200053382A1

公开(公告)日：2020-02-13

申请号：US16660071

申请日：2019-10-22

Applicant: Panasonic Intellectual Property Corporation of America

Inventor： Kiyofumi ABE ,  Takahiro NISHI ,  Tadamasa TOMA ,  Ryuichi KANOH ,  Takashi HASHIMOTO

IPC: H04N19/52 ,  H04N19/59 ,  H04N19/105 ,  H04N19/176

Abstract: An encoder that; obtains two prediction images by performing motion compensation using two motion vectors; obtains a gradient value of each of pixels included in the two prediction images; derives a local motion estimation value for each of sub-blocks based on the pixel value and the gradient value of each of the pixels, the sub-blocks being obtained by partitioning the current block; and generates a final prediction image for the current block using the pixel value and the gradient value of each of the pixels, and the local motion estimation value derived for each of the sub-blocks. Each of the pixels in the two prediction images is interpolated with sub-pixel accuracy, and a reference range for the interpolation is included in a normal reference range that is referred to for motion compensation for the current block in normal inter prediction performed without using the local motion estimation value.

公开(公告)号：US20190191160A1

公开(公告)日：2019-06-20

申请号：US16268979

申请日：2019-02-06

Applicant: Panasonic Intellectual Property Corporation of America

Inventor： Kiyofumi ABE ,  Takahiro NISHI ,  Takashi HASHIMOTO ,  Tadamasa TOMA

IPC: H04N19/122 ,  H04N19/13 ,  H04N19/159 ,  H04N19/124 ,  H04N19/176 ,  H04N19/18 ,  H04N19/61 ,  H04N19/146

CPC classification number: H04N19/122 ,  H04N19/124 ,  H04N19/13 ,  H04N19/136 ,  H04N19/146 ,  H04N19/159 ,  H04N19/176 ,  H04N19/18 ,  H04N19/61

Abstract: An encoder which encodes image information includes memory and circuitry accessible to the memory. The circuitry binarizes a data value indicating the number of non-zero coefficients included in a current basic block which is one of one or more basic blocks in a frequency transform block, according to a conversion table, to encode the image information which includes the data value. When binarizing the data value, the circuitry selects the conversion table from a plurality of tables including two or more tables which differ from each other in difference between a longest bit length and a shortest bit length of a plurality of binary values associated with a plurality of data values, according to the position of the current basic block in the current frequency transform block which is the frequency transform block including the current basic block, and binarizes the data value according to the conversion table selected.

公开(公告)号：US20190174132A1

公开(公告)日：2019-06-06

申请号：US16269060

申请日：2019-02-06

Applicant: Panasonic Intellectual Property Corporation of America

Inventor： Kiyofumi ABE ,  Takahiro NISHI ,  Takashi HASHIMOTO ,  Tadamasa TOMA

IPC: H04N19/13 ,  H04N19/129

Abstract: An encoder which encodes image information includes memory and circuitry accessible to the memory. The circuitry accessible to the memory: encodes position information indicating the position of a specific basic block which is a basic block including a non-zero coefficient first in a predetermined scan order defined in a descending order of frequencies of one or more basic blocks included in a frequency transform block composed of a plurality of frequency transform coefficients; and encodes only block information indicating a plurality of frequency transform coefficients of each of the specific basic block and a following basic block in the predetermined scan order.

公开(公告)号：US20190174131A1

公开(公告)日：2019-06-06

申请号：US16269018

申请日：2019-02-06

Applicant: Panasonic Intellectual Property Corporation of America

Inventor： Kiyofumi ABE ,  Takahiro NISHI ,  Takashi HASHIMOTO ,  Tadamasa TOMA

IPC: H04N19/13 ,  H04N19/157

Abstract: An encoder includes memory and circuitry accessible to the memory. The circuitry accessible to the memory: switches whether or not to apply arithmetic encoding to a binary data string in which image information has been binarized; binarizes frequency transform coefficient information according to different binarization formats between when arithmetic encoding is applied to the binary data string and when arithmetic encoding is not applied to the binary data string; and binarizes a part or the entirety of prediction parameter information according to a binarization format which is common between when arithmetic encoding is applied to the binary data string and when arithmetic encoding is not applied to the binary data string.