Method and apparatus for increased communication channel pre-emphasis for clock-like data patterns
    21.
    发明授权
    Method and apparatus for increased communication channel pre-emphasis for clock-like data patterns 有权
    用于增加用于时钟状数据模式的通信信道预加重的方法和装置

    公开(公告)号:US07869540B2

    公开(公告)日:2011-01-11

    申请号:US11506536

    申请日:2006-08-18

    IPC分类号: H04L25/49 H04L25/03 H04K1/02

    摘要: Methods and apparatus are disclosed for increased pre-emphasis for clock-like data patterns to compensate for channel distortions. One aspect of the invention compensates for channel distortions by evaluating a data pattern to be transmitted; determining if the data pattern satisfies one or more predefined criteria defining a clock-like data pattern; and generating a pre-emphasis level for the clock-like data patterns that is higher than a pre-emphasis level for the data patterns that do not satisfy the one or more predefined criteria. For example, a predefined window size can be defined for determining if the data pattern satisfies the one or more predefined criteria defining the clock-like data pattern. In one exemplary implementation, the higher pre-emphasis level is generated for one or more predefined data patterns. A table can optionally be accessed to determine the pre-emphasis level based on the data pattern.

    摘要翻译: 公开了用于增加对时钟状数据模式的预加重以补偿信道失真的方法和装置。 本发明的一个方面通过评估要发送的数据模式来补偿信道失真; 确定数据模式是否满足定义时钟状数据模式的一个或多个预定标准; 以及对于不满足一个或多个预定标准的数据模式的高于预加重级别的时钟状数据模式,生成预加重级别。 例如,可以定义预定窗口大小以确定数据模式是否满足定义时钟状数据模式的一个或多个预定标准。 在一个示例性实现中,为一个或多个预定义的数据模式生成较高的预加重级别。 可以可选地访问表以基于数据模式确定预加重级别。

    Compensation Techniques for Reducing Power Consumption in Digital Circuitry
    22.
    发明申请
    Compensation Techniques for Reducing Power Consumption in Digital Circuitry 有权
    降低数字电路功耗的补偿技术

    公开(公告)号:US20100244937A1

    公开(公告)日:2010-09-30

    申请号:US12160373

    申请日:2007-10-31

    IPC分类号: G05F1/10

    CPC分类号: H03K19/00369

    摘要: A compensation circuit for reducing power consumption in at least one digital circuit includes a first sample circuit connected to a first supply voltage, a second sample circuit connected to a second supply voltage, and a controller connected to the first and second sample circuits. The first and second sample circuits are substantially functionally equivalent to one another but optimized for different regions of operation within a specified range of PVT conditions. The controller is operative to receive respective output signals from the first and second sample circuits, to monitor a functionality of the second sample circuit relative to the first sample circuit, and to adjust a level of the second supply voltage to ensure correct operation of the second sample circuit throughout the specified range of PVT conditions. The digital circuit is operative from the second supply voltage.

    摘要翻译: 用于降低至少一个数字电路中的功耗的补偿电路包括连接到第一电源电压的第一采样电路,连接到第二电源电压的第二采样电路和连接到第一和第二采样电路的控制器。 第一和第二采样电路基本上在功能上彼此相等,但是在PVT条件的指定范围内针对不同操作区域进行了优化。 控制器可操作以从第一和第二采样电路接收相应的输出信号,以监测第二采样电路相对于第一采样电路的功能,并调整第二电源电压的电平,以确保第二采样电路的正常工作 采样电路在指定的PVT条件范围内。 数字电路从第二电源电压工作。

    Method and apparatus for adjusting receiver gain based on received signal envelope detection
    23.
    发明授权
    Method and apparatus for adjusting receiver gain based on received signal envelope detection 失效
    基于接收信号包络检测来调整接收机增益的方法和装置

    公开(公告)号:US07738605B2

    公开(公告)日:2010-06-15

    申请号:US11318953

    申请日:2005-12-23

    IPC分类号: H04L27/08

    摘要: Methods and apparatus are provided for adjusting receiver gain based on received signal envelope detection. The gain of a received signal is adjusted by obtaining a plurality of samples of the received signal for a given unit interval; determining an amplitude of the received signal based on the samples; and adjusting a receiver gain based on the determined amplitude. The received signal can be sampled, for example, using a plurality of latches. The value of the received signal can then be estimated by evaluating one or more of the latch values. Once the amplitude of the received signal is determined, one or more latches can be positioned at a desired target amplitude and the receiver gain can be adjusted until the amplitude of the received signal is within a desired tolerance of the specified target value.

    摘要翻译: 提供了基于接收信号包络检测来调整接收机增益的方法和装置。 通过获得给定单位间隔的接收信号的多个样本来调整接收信号的增益; 基于样本确定接收信号的幅度; 以及基于所确定的幅度来调整接收机增益。 可以例如使用多个锁存器对接收到的信号进行采样。 然后可以通过评估一个或多个锁存值来估计接收信号的值。 一旦确定了接收信号的幅度,就可以将一个或多个锁存器定位在期望的目标幅度,并且可以调整接收器增益,直到接收到的信号的振幅在指定的目标值的期望公差内。

    Method and Apparatus for Digital VCDL Startup
    24.
    发明申请
    Method and Apparatus for Digital VCDL Startup 有权
    数字VCDL启动方法与装置

    公开(公告)号:US20090167379A1

    公开(公告)日:2009-07-02

    申请号:US11967619

    申请日:2007-12-31

    IPC分类号: H03L7/06

    CPC分类号: H03L7/0812

    摘要: Methods and apparatus are provided fox improved startup of a voltage controlled delay loop that has an injection clock and a return clock. A control signal is determined for a plurality of delay elements in a voltage controlled delay loop by obtaining a histogram count of a number of occurrences of at least one predefined logic value for a plurality of delay settings of the voltage controlled delay loop; determining a histogram count that approximately corresponds to an alignment of at least one edge in the injection and return clocks; and determining the control signal based on the determined histogram count that approximately corresponds to the alignment. The control signal can be, for example, a delay control current or a delay control voltage. The voltage controlled delay loop can be started using the determined control signal. The histogram count can be obtained for a plurality of PVT combinations and the control signal can then be determined for each PVT combination. The determined control signal can optionally be stored in a table for each of the plurality of PVT combinations

    摘要翻译: 提供了具有注入时钟和返回时钟的电压控制延迟回路的改进的启动方法和装置。 通过获得针对电压控制的延迟环路的多个延迟设置的至少一个预定逻辑值的出现次数的直方图计数,为电压控制的延迟环路中的多个延迟元件确定控制信号; 确定近似对应于所述注入和返回时钟中的至少一个边缘的对准的直方图计数; 以及基于大致对应于所述对准的所确定的直方图计数来确定所述控制信号。 控制信号可以是例如延迟控制电流或延迟控制电压。 可以使用所确定的控制信号来开始压控延迟环路。 可以为多个PVT组合获得直方图计数,然后可以为每个PVT组合确定控制信号。 所确定的控制信号可以可选地存储在用于多个PVT组合中的每一个的表中

    Methods and apparatus for evaluating the eye margin of a communications device using a data eye monitor
    25.
    发明申请
    Methods and apparatus for evaluating the eye margin of a communications device using a data eye monitor 有权
    使用数据眼监视器评估通信设备的眼边的方法和装置

    公开(公告)号:US20070268962A1

    公开(公告)日:2007-11-22

    申请号:US11434688

    申请日:2006-05-16

    IPC分类号: H04B17/00

    CPC分类号: H04L1/20 H04B17/309

    摘要: Methods and apparatus are provided for evaluating the eye margin of a communications device using a data eye monitor. The quality of a data eye associated with a signal is evaluated by sampling the signal for a plurality of different phases; evaluating the samples to evaluate one or more of a height and width of the data eye; and determining whether the one or more of the height and width satisfy one or more predefined criteria. One or more parameters of the communications device can optionally be adjusted if the communications device does not satisfy the one or more predefined criteria. The communications device can optionally be assigned to a quality category based on the evaluation. A phase offset between a first clock signal used to sample the signal and one or more clocks used to sample data is reduced.

    摘要翻译: 提供的方法和装置用于评估使用数据眼监护仪的通信设备的眼部边缘。 与信号相关联的数据眼的质量通过对多个不同相位的信号进行采样来评估; 评估样本以评估数据眼睛的高度和宽度中的一个或多个; 以及确定所述高度和宽度中的一个或多个是否满足一个或多个预定标准。 如果通信设备不满足一个或多个预定标准,则可以可选地调整通信设备的一个或多个参数。 可以根据评估可选地将通信设备分配给质量类别。 减少用于采样信号的第一时钟信号与用于采样数据的一个或多个时钟之间的相位偏移。

    Methods and apparatus for adaptive link partner transmitter equalization
    26.
    发明授权
    Methods and apparatus for adaptive link partner transmitter equalization 有权
    自适应链路伙伴发射机均衡的方法和装置

    公开(公告)号:US08320439B2

    公开(公告)日:2012-11-27

    申请号:US12040575

    申请日:2008-02-29

    IPC分类号: H03H7/30

    摘要: Methods and apparatus are provided for adaptive link partner transmitter equalization. According to one aspect of the invention, a local transceiver adapts one or more equalization parameters of a link partner by receiving a training frame over a channel between the link partner and the local transceiver, wherein the training frame is comprised of a predefined training pattern; adjusting one or more of the equalization parameters of the link partner; and determining whether the equalization of the channel satisfies one or more predefined criteria based on whether the predefined training pattern is properly received by the local transceiver. The predefined training pattern can be a pseudo random pattern, such as a PN11 pattern Noise margins and jitters margins for the channel can optionally be improved.

    摘要翻译: 为自适应链路伙伴发射机均衡提供了方法和装置。 根据本发明的一个方面,本地收发器通过在链路伙伴和本地收发信机之间的信道上接收训练帧来适配链路伙伴的一个或多个均衡参数,其中训练帧由预定义的训练模式组成; 调整所述链路伙伴的一个或多个均衡参数; 以及基于所述本地收发器是否适当地接收了所述预定训练模式,确定所述信道的均衡是否满足一个或多个预定标准。 预定义的训练模式可以是伪随机模式,例如PN11模式,可以可选地提高通道的噪声余量和抖动余量。

    Method and Apparatus for Regulating a Power Supply of an Integrated Circuit
    27.
    发明申请
    Method and Apparatus for Regulating a Power Supply of an Integrated Circuit 有权
    用于调节集成电路电源的方法和装置

    公开(公告)号:US20120068762A1

    公开(公告)日:2012-03-22

    申请号:US13304759

    申请日:2011-11-28

    IPC分类号: H02J4/00

    CPC分类号: H02J1/00

    摘要: Disclosed is a circuit for adjusting a voltage supplied to an IC by a power supply circuit that produces a regulated-output voltage based on an output-control signal generated by a resistive voltage divider. The circuit includes a PVT detector configured to generate an interface control signal and an interface circuit (i) connected to PVT detector and to the resistive voltage divider and (ii) configured to adjust its resistance in response to the interface control signal. Adjusting the resistance of the interface circuit causes the voltage of the output-control signal to be adjusted, thus causing the power supply circuit to adjust the regulated output voltage.

    摘要翻译: 公开了一种用于通过电源电路来调节提供给IC的电压的电路,该电源电路基于由电阻分压器产生的输出控制信号产生调节输出电压。 电路包括配置成产生接口控制信号的PVT检测器和连接到PVT检测器和电阻分压器的接口电路(i),以及(ii)被配置为响应于接口控制信号调整其电阻。 调整接口电路的电阻可以调节输出控制信号的电压,从而使电源电路调整稳压输出电压。

    Method and apparatus for detecting and adjusting characteristics of a signal
    28.
    发明授权
    Method and apparatus for detecting and adjusting characteristics of a signal 失效
    用于检测和调整信号特性的方法和装置

    公开(公告)号:US07977989B2

    公开(公告)日:2011-07-12

    申请号:US12730671

    申请日:2010-03-24

    IPC分类号: H03K5/12

    摘要: Disclosed is a circuit that adjusts a characteristic of a signal transmitted from a transmitter to a receiver over a communication channel (e.g., a wire, a backplane, etc.). The circuit includes a latch that receives the signal at a predetermined point in the circuit and samples a voltage of the signal many times after a threshold voltage is applied to the latch. The circuit also includes a processor that determines the characteristic of the signal when the sampled voltages indicate a transition point and that adjusts the threshold voltage when the sampled voltages do not indicate a transition point. The processor adjusts the characteristic of the signal by adjusting at least one of a current and a voltage of the transmitter when the characteristic of the signal is outside a predetermined range.

    摘要翻译: 公开了一种通过通信信道(例如,线,背板等)调整从发射机发射到接收机的信号的特性的电路。 该电路包括一个锁存器,该锁存器在阈值电压施加到锁存器之后多次接收电路中预定点处的信号并对信号的电压进行多次采样。 该电路还包括一个处理器,当采样电压指示转换点时,确定信号的特性,并且当采样电压不指示转换点时调整阈值电压。 当信号的特性在预定范围之外时,处理器通过调节发射机的电流和电压中的至少一个来调整信号的特性。

    METHOD AND APPARATUS FOR DIGITAL VCDL STARTUP
    29.
    发明申请
    METHOD AND APPARATUS FOR DIGITAL VCDL STARTUP 失效
    数字VCDL启动的方法与装置

    公开(公告)号:US20100237915A1

    公开(公告)日:2010-09-23

    申请号:US12789544

    申请日:2010-05-28

    IPC分类号: H03L7/06

    CPC分类号: H03L7/0812

    摘要: Methods and apparatus are provided for improved startup of a voltage controlled delay loop that has an injection clock and a return clock. A control signal is determined for a plurality of delay elements in a voltage controlled delay loop by obtaining a histogram count of a number of occurrences of at least one predefined logic value for a plurality of delay settings of the voltage controlled delay loop; determining a histogram count that approximately corresponds to an alignment of at least one edge in the injection and return clocks; and determining the control signal based on the determined histogram count that approximately corresponds to the alignment. The voltage controlled delay loop can be started using the deter wined control signal. The histogram count can be obtained for a plurality of PVT combinations and the control signal can then be determined for each PVT combination.

    摘要翻译: 提供了用于改进启动具有注入时钟和返回时钟的电压控制延迟回路的方法和装置。 通过获得针对电压控制的延迟环路的多个延迟设置的至少一个预定逻辑值的出现次数的直方图计数,为电压控制的延迟环路中的多个延迟元件确定控制信号; 确定近似对应于所述注入和返回时钟中的至少一个边缘的对准的直方图计数; 以及基于大致对应于所述对准的所确定的直方图计数来确定所述控制信号。 电压控制延迟环可以使用阻尼控制信号启动。 可以为多个PVT组合获得直方图计数,然后可以为每个PVT组合确定控制信号。