公开(公告)号：US08798222B2

公开(公告)日：2014-08-05

申请号：US11095770

申请日：2005-03-31

申请人： Mohammad S. Mobin ,  Gregory W. Sheets ,  Lane A. Smith ,  Craig B. Ziemer

发明人： Mohammad S. Mobin ,  Gregory W. Sheets ,  Lane A. Smith ,  Craig B. Ziemer

IPC分类号： H04L7/00

CPC分类号： H03K5/13 ,  H03K2005/00052 ,  H04L7/00

摘要： Methods and apparatus are provided for digital linearization of an analog phase interpolator. Up to 2N desired phase values are mapped to a corresponding M bit value, where M is greater than N. A corresponding M bit value is applied to the phase interpolator to obtain a desired one of the 2N desired phase values. A linearized phase interpolator is also provided that accounts for process, voltage, temperature or aging (PVTA) variations.

摘要翻译： 提供了用于模拟相位内插器的数字线性化的方法和装置。 多达2N个所需的相位值被映射到对应的M位值，其中M大于N.相应的M位值被施加到相位内插器以获得期望的2N个期望相位值。 还提供了线性化相位内插器，其考虑过程，电压，温度或老化（PVTA）变化。

公开(公告)号：US20070268962A1

公开(公告)日：2007-11-22

申请号：US11434688

申请日：2006-05-16

申请人： Mohammad S. Mobin ,  Gregory W. Sheets ,  Lane A. Smith ,  Craig B. Ziemer

发明人： Mohammad S. Mobin ,  Gregory W. Sheets ,  Lane A. Smith ,  Craig B. Ziemer

IPC分类号： H04B17/00

CPC分类号： H04L1/20 ,  H04B17/309

摘要： Methods and apparatus are provided for evaluating the eye margin of a communications device using a data eye monitor. The quality of a data eye associated with a signal is evaluated by sampling the signal for a plurality of different phases; evaluating the samples to evaluate one or more of a height and width of the data eye; and determining whether the one or more of the height and width satisfy one or more predefined criteria. One or more parameters of the communications device can optionally be adjusted if the communications device does not satisfy the one or more predefined criteria. The communications device can optionally be assigned to a quality category based on the evaluation. A phase offset between a first clock signal used to sample the signal and one or more clocks used to sample data is reduced.

摘要翻译： 提供的方法和装置用于评估使用数据眼监护仪的通信设备的眼部边缘。 与信号相关联的数据眼的质量通过对多个不同相位的信号进行采样来评估; 评估样本以评估数据眼睛的高度和宽度中的一个或多个; 以及确定所述高度和宽度中的一个或多个是否满足一个或多个预定标准。 如果通信设备不满足一个或多个预定标准，则可以可选地调整通信设备的一个或多个参数。 可以根据评估可选地将通信设备分配给质量类别。 减少用于采样信号的第一时钟信号与用于采样数据的一个或多个时钟之间的相位偏移。

公开(公告)号：US07312667B2

公开(公告)日：2007-12-25

申请号：US11221316

申请日：2005-09-07

申请人： Mohammad S. Mobin ,  Gregory W. Sheets ,  Vladimir Sindalovsky ,  Lane A. Smith ,  Craig B. Ziemer

发明人： Mohammad S. Mobin ,  Gregory W. Sheets ,  Vladimir Sindalovsky ,  Lane A. Smith ,  Craig B. Ziemer

IPC分类号： H03B27/00

CPC分类号： H03L7/00 ,  H04L7/0337

摘要： The present invention addresses the generation of a controlled clock source for use in trimming VCDL delay line output clocks. In this trimming process, adjustments are made for static variations in these output clocks. The invention's use of a controlled clock source eliminates the need for this trimming process to be conducted in real time and reduces the expense of the circuitry required.

摘要翻译： 本发明解决了用于微调VCDL延迟线输出时钟的受控时钟源的产生。 在这个修整过程中，对这些输出时钟的静态变化进行调整。 本发明使用受控的时钟源消除了对该修整过程的实时性的需要，并且降低了所需电路的费用。

公开(公告)号：US08126039B2

公开(公告)日：2012-02-28

申请号：US11434688

申请日：2006-05-16

申请人： Mohammad S. Mobin ,  Gregory W. Sheets ,  Lane A. Smith ,  Craig B. Ziemer

发明人： Mohammad S. Mobin ,  Gregory W. Sheets ,  Lane A. Smith ,  Craig B. Ziemer

IPC分类号： H04B3/46

CPC分类号： H04L1/20 ,  H04B17/309

摘要： Methods and apparatus are provided for evaluating the eye margin of a communications device using a data eye monitor. The quality of a data eye associated with a signal is evaluated by sampling the signal for a plurality of different phases; evaluating the samples to evaluate one or more of a height and width of the data eye; and determining whether the one or more of the height and width satisfy one or more predefined criteria. One or more parameters of the communications device can optionally be adjusted if the communications device does not satisfy the one or more predefined criteria. The communications device can optionally be assigned to a quality category based on the evaluation. A phase offset between a first clock signal used to sample the signal and one or more clocks used to sample data is reduced.

摘要翻译： 提供的方法和装置用于评估使用数据眼监护仪的通信设备的眼部边缘。 与信号相关联的数据眼的质量通过对多个不同相位的信号进行采样来评估; 评估样本以评估数据眼睛的高度和宽度中的一个或多个; 以及确定所述高度和宽度中的一个或多个是否满足一个或多个预定标准。 如果通信设备不满足一个或多个预定标准，则可以可选地调整通信设备的一个或多个参数。 可以根据评估可选地将通信设备分配给质量类别。 减少用于采样信号的第一时钟信号与用于采样数据的一个或多个时钟之间的相位偏移。

公开(公告)号：US07787515B2

公开(公告)日：2010-08-31

申请号：US11353431

申请日：2006-02-14

申请人： Mohammad S. Mobin ,  Gregory W. Sheets ,  Vladimir Sindalovsky ,  William B. Wilson ,  Craig B. Ziemer

发明人： Mohammad S. Mobin ,  Gregory W. Sheets ,  Vladimir Sindalovsky ,  William B. Wilson ,  Craig B. Ziemer

IPC分类号： H04B1/00

CPC分类号： H04L27/0014 ,  H04B1/7075 ,  H04L2027/0036

摘要： A circuit for spread spectrum rate control uses a first interpolator to phase interpolate between a first signal and a second signal and generate a first output signal based on a first control signal. A second interpolator is utilized to phase interpolate between a third signal and a fourth signal and generate a second output signal based on a second control signal. A multiplexer is used to select, based on a select signal, the first output signal or the second output signal as a spread spectrum clock (SSCLK). A leap-frog interpolator control is used to generate, in synchronism with the SSCLK, the first control signal based on a first type of phase adjustment request, the second control signal based on a second type of phase adjustment request, and the select signal to switch the multiplexer between the first output signal and the second output signal after allowing for an interpolator settling time when changing the first control signal or the second control signal.

摘要翻译： 用于扩频率控制的电路使用第一内插器在第一信号和第二信号之间进行相位插值，并且基于第一控制信号产生第一输出信号。 第二内插器用于在第三信号和第四信号之间进行相位插值，并且基于第二控制信号产生第二输出信号。 多路复用器用于基于选择信号选择第一输出信号或第二输出信号作为扩频时钟（SSCLK）。 跳跃内插器控制用于与SSCLK同步地产生基于第一类型的相位调整请求的第一控制信号，基于第二类型的相位调整请求的第二控制信号，以及选择信号 在改变第一控制信号或第二控制信号之后允许内插器稳定时间之后，在第一输出信号和第二输出信号之间切换多路复用器。

公开(公告)号：US07190198B2

公开(公告)日：2007-03-13

申请号：US10999889

申请日：2004-11-30

申请人： Ronald L. Freyman ,  Vladimir Sindalovsky ,  Lane A. Smith ,  Craig B. Ziemer

发明人： Ronald L. Freyman ,  Vladimir Sindalovsky ,  Lane A. Smith ,  Craig B. Ziemer

IPC分类号： H03L7/06

CPC分类号： G06F1/04

摘要： A voltage controlled delay loop and method are disclosed for clock and data recovery applications. The voltage controlled delay loop generates clock signals having similar frequency and different phases. The voltage controlled delay loop comprises at least one delay element to generate at least two phases of a reference clock; a central interpolator for interpolating the at least two phases of the reference clock to generate an interpolated signal; and an input that injects the interpolated signal into a delay stage. The central interpolator provides a fine phase control. In addition, a coarse phase control can optionally be achieved by selectively injecting the interpolated signal into a given delay stage. A further voltage controlled delay loop is disclosed with coarse and fine phase control using a number of interpolators.

摘要翻译： 公开了用于时钟和数据恢复应用的电压控制延迟环路和方法。 电压控制延迟环路产生具有相似频率和不同相位的时钟信号。 电压控制延迟回路包括至少一个延迟元件以产生参考时钟的至少两个相位; 中央内插器，用于内插参考时钟的至少两个相位以产生内插信号; 以及将内插信号注入延迟级的输入。 中央插值器提供精细的相位控制。 此外，可以通过选择性地将内插信号注入到给定的延迟级中来可选地实现粗略的相位控制。 公开了使用多个内插器的粗略和精细相位控制的另一个电压控制延迟回路。

公开(公告)号：US07778377B2

公开(公告)日：2010-08-17

申请号：US11141695

申请日：2005-05-31

申请人： Vladimir Sindalovsky ,  Lane A. Smith ,  Craig B. Ziemer

发明人： Vladimir Sindalovsky ,  Lane A. Smith ,  Craig B. Ziemer

IPC分类号： H03D3/24

CPC分类号： H04B15/02 ,  H04B2215/067

摘要： Methods and apparatus are provided for generating a frequency with a predefined offset from a reference frequency. A spread spectrum generator circuit is disclosed that comprises a voltage controlled delay loop for generating a plurality of signals having a different phase; and at least one interpolator for processing at least two of the signals to generate an output signal having a phase between a phase of the at least two of the signals, wherein the output is varied between a phase of the at least two of the signals to generate the spread spectrum. A spread spectrum having a frequency lower than an applied clock signal is generated using a continuous phase delay increase and a spread spectrum having a frequency higher than the clock signal is generated using a continuous phase delay decrease.

摘要翻译： 提供了用于产生具有与参考频率的预定义偏移的频率的方法和装置。 公开了一种扩频发生器电路，其包括用于产生具有不同相位的多个信号的电压控制延迟环路; 以及至少一个内插器，用于处理至少两个所述信号以产生具有所述至少两个所述信号的相位之间的相位的输出信号，其中所述输出在所述至少两个信号的相位之间变化 生成扩频。 使用连续的相位延迟增加来产生频率低于所施加的时钟信号的扩展频谱，并且使用连续的相位延迟减小产生具有高于时钟信号的频率的扩频。

公开(公告)号：US07205811B2

公开(公告)日：2007-04-17

申请号：US11095772

申请日：2005-03-31

申请人： Ronald L. Freyman ,  Craig B. Ziemer

发明人： Ronald L. Freyman ,  Craig B. Ziemer

IPC分类号： H03K5/13

CPC分类号： H03K6/04

摘要： Methods and apparatus are provided for maintaining a desired slope of clock edges in a phase interpolator using an adjustable bias. The disclosed phase interpolator comprises at least one delay element to generate at least two interpolation signals each having an associated phase and a variable slope unit associated with each of the at least two interpolation signals, wherein a slope of each of the variable slope units is controlled by a bias signal and is varied based on a data rate of the interpolation signals. The slope is varied to maintain a desired slope of clock edges associated with the interpolation signals. The slope can be maintained, for example, between approximately the value of the delay between consecutive clock edges and twice the value of the delay between consecutive clock edges.

摘要翻译： 提供的方法和装置用于使用可调偏置来保持相位插值器中的时钟边缘的期望斜率。 所公开的相位插值器包括至少一个延迟元件，以产生每个具有相关联的相关联的至少两个插值信号和与至少两个内插信号中的每一个相关联的可变斜率单元，其中每个可变斜率单元的斜率被控制 通过偏置信号，并且基于插值信号的数据速率而变化。 改变斜率以保持与内插信号相关联的时钟边缘的期望斜率。 斜率可以维持在例如在连续时钟边缘之间的延迟的近似值和连续时钟边缘之间的延迟值的两倍之间。

公开(公告)号：US07236037B2

公开(公告)日：2007-06-26

申请号：US11138777

申请日：2005-05-26

申请人： Christopher J. Abel ,  Vladimir Sindalovsky ,  Craig B. Ziemer

发明人： Christopher J. Abel ,  Vladimir Sindalovsky ,  Craig B. Ziemer

IPC分类号： H03K3/00

CPC分类号： H04L7/0025 ,  H03L7/07 ,  H03L7/0814 ,  H04L7/0337

摘要： A delay loop (e.g., a voltage-controlled delay loop) has (at least) two devices (e.g., interpolators) for generating clock signals for injection into the delay elements of the delay loop in a leap-frog manner, in which, while one interpolator is generating the clock signal currently selected for injection, the other interpolator can be controlled to generate the next clock signal to be selected for injection. This leap-frog technique can provide more settling time for generating injected clock signals than implementations that rely on a single interpolator.

摘要翻译： 延迟环路（例如，电压控制延迟环路）具有（至少）两个用于产生用于以跳跃方式注入到延迟环路的延迟元件中的时钟信号的器件（例如，内插器），其中， 一个内插器正在产生当前被选择用于注入的时钟信号，另一个内插器可被控制以产生要被选择用于注入的下一个时钟信号。 这种跳跃式技术可以提供更多的建立时间来产生注入的时钟信号，而不是依赖于单个内插器的实现。

公开(公告)号：US06381086B1

公开(公告)日：2002-04-30

申请号：US09607337

申请日：2000-10-23

申请人： Reed H. Koenig ,  Craig B. Ziemer

发明人： Reed H. Koenig ,  Craig B. Ziemer

IPC分类号： G11B502

CPC分类号： G11B5/022 ,  G11B5/012 ,  G11B5/02 ,  G11B2005/0013

摘要： Programmable active damping of the overshoot in the bipolar write driver output current waveform in the write head of a hard disk drive is provided by subtracting, a controlled amount of current from the writer current, for a predetermined duration, at the beginning of each transition of the write driver output current.

摘要翻译： 在硬盘驱动器的写入头中的双极性写入驱动器输出电流波形中的过冲的可编程有源阻尼是通过从每个转换开始时从写入器电流中减去一个受控量的电流达预定的持续时间 写驱动器输出电流。