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    2-BIT HIGH-POWER AMPLIFYING NON-RECIPROCAL REFLECTIVE METASURFACE
    1.
    发明公开
    2-BIT HIGH-POWER AMPLIFYING NON-RECIPROCAL REFLECTIVE METASURFACE 审中-公开

    公开(公告)号：US20240235537A1

    公开(公告)日：2024-07-11

    申请号：US18404899

    申请日：2024-01-05

    申请人： Xidian University

    发明人： Long LI ,  Guanxuan LI ,  Xin WANG ,  Dexiao XIA ,  Ruijie LI ,  Haixia LIU

    IPC分类号： H03K5/02 ,  H01P1/00 ,  H01P1/16 ,  H01P1/185

    CPC分类号： H03K5/02 ,  H01P1/005 ,  H01P1/16 ,  H01P1/185

    摘要： A 2-bit high-power amplifying non-reciprocal reflective metasurface is provided. The metasurface comprises a plurality of metasurface units distributed in an array; each metasurface unit comprises a first metal layer, an intermediate layer, and a second metal layer which are sequentially stacked; the second metal layer comprises a receiving metal patch and a transmitting metal patch; two diodes are both positioned on a longitudinal central axis of the receiving metal patch; orientation of the slot on the transmitting metal patch is orthogonal to orientation of the slot on the receiving metal patch; the first metal layer comprises a phase shifter, which comprises first series diodes and second series diodes forming a reconfigurable 90-degree phase-shift circuit.

    Routing integrated circuit element
    2.
    发明授权
    Routing integrated circuit element 有权

    公开(公告)号：US11955975B2

    公开(公告)日：2024-04-09

    申请号：US17553981

    申请日：2021-12-17

    申请人： LeRain Technology Co., Ltd.

    发明人： Miaobin Gao ,  Chia-Chi Hu

    IPC分类号： H03K5/02 ,  H01L23/49 ,  H04Q11/04

    CPC分类号： H03K5/02 ,  H01L23/49 ,  H04Q11/0471

    摘要： A routing integrated circuit element is disclosed. The routing integrated circuit element is connected between a first and a second electronic module and includes a body, a first, and a second buffer element. A first side of the body is connected to the first electronic module. A second side is connected to the second electronic module and located on a different side from the first side. The distance between the second side and the second electronic module is shorter than the distance between the second side and the first electronic module. The first buffer element transmits an electronic signal from the first side to the second side. The second buffer element transmits the electronic signal from the second side to the first side, wherein the transmission directions of the electronic signals transmitted by the first buffer element and the second buffer element are opposite.

    High frequency resolution digital sinusoid generator
    4.
    发明授权
    High frequency resolution digital sinusoid generator 有权

    公开(公告)号：US11689191B2

    公开(公告)日：2023-06-27

    申请号：US17673214

    申请日：2022-02-16

    申请人： STMicroelectronics International N.V.

    发明人： Ankur Bal

    IPC分类号： H03K5/00 ,  H03K5/02

    CPC分类号： H03K5/02 ,  H03K2005/00078

    摘要： A delay circuit applies a one sample delay to a first digital sinusoid signal and outputs a delayed digital sinusoid signal. The first digital sinusoid signal and the delayed digital sinusoid signal are then added to each other by an adder circuit to generate an added digital sinusoid signal. A gain scaling circuit applies a scaling factor to the added digital sinusoid signal to generate a second digital sinusoid signal. Samples of the first and second digital sinusoid signals are alternately selected by a multiplexing circuit to generate a third digital sinusoid signal having twice as many samples as the first digital sinusoid signal over a same sinusoid period.

    MULTIPHASE CLOCK GENERATORS WITH DIGITAL CALIBRATION
    5.
    发明公开
    MULTIPHASE CLOCK GENERATORS WITH DIGITAL CALIBRATION 审中-公开

    公开(公告)号：US20230198734A1

    公开(公告)日：2023-06-22

    申请号：US17644693

    申请日：2021-12-16

    申请人： Analog Devices, Inc.

    发明人： Michael St. Germain ,  John Kenney

    IPC分类号： H04L7/04 ,  H03K5/02

    CPC分类号： H04L7/04 ,  H03K5/02

    摘要： Apparatus and methods for multiphase clock generation are provided herein. In certain embodiments, a multiphase clock generator includes a first clock buffer that generates a first output clock signal based on a first input clock signal, a second clock buffer that generates a second output clock signal based on a second input clock signal, and a first clock interpolation circuit that generates a third output clock signal based on interpolating the first input clock signal and the second input clock signal. The first clock interpolation circuit generates the third output clock signal based on multiplying the first input clock signal by a first adjustable current to generate a first multiplied current, multiplying the second input clock signal by a second adjustable current to generate a second multiplied current, combining the first multiplied current and the second multiplied current to generate a combined current, and integrating the combined current.

    Linear high voltage driver with programmable differential and common mode gain
    6.
    发明授权
    Linear high voltage driver with programmable differential and common mode gain 有权

    公开(公告)号：US10075139B2

    公开(公告)日：2018-09-11

    申请号：US15346064

    申请日：2016-11-08

    申请人： STMicroelectronics, Inc.

    发明人： Pavan Nallamothu

    IPC分类号： H03K3/00 ,  H03G3/00 ,  H03K5/02 ,  H03K17/687

    CPC分类号： H03G3/001 ,  H03K5/02 ,  H03K17/6872

    摘要： A low voltage to high voltage (LV2HV) conversion circuit has an input configured to receive an input signal (at a relatively low voltage) and an output configured to generate an output signal (at a relatively high voltage). The LV2HV conversion circuit includes a voltage to current conversion circuit referenced to the relatively low voltage and configured to convert a voltage of the input signal to a first current, wherein a magnitude of the first current is dependent on said voltage of the input signal and a gain setting value. A current mirroring circuit mirrors the first current and outputs a second current. A current to voltage conversion circuit converts the second current to a voltage of the output signal. The current mirroring circuit and current to voltage conversion circuit are referenced to the relatively high voltage.

    POWER AMPLIFYING DEVICE
    7.
    发明申请
    POWER AMPLIFYING DEVICE 审中-公开

    公开(公告)号：US20180191316A1

    公开(公告)日：2018-07-05

    申请号：US15736327

    申请日：2016-06-09

    申请人： HITACHI KOKUSAI ELECTRIC INC.

    发明人： Kenya TOMARU ,  Manabu NAKAMURA

    IPC分类号： H03F3/217 ,  H03F3/24 ,  H03K5/02 ,  H03M1/06 ,  H04L27/36

    CPC分类号： H03F3/2173 ,  H03F3/217 ,  H03F3/2171 ,  H03F3/2175 ,  H03F3/24 ,  H03K5/02 ,  H03M1/0629 ,  H04L27/362

    摘要： An outphasing power amplifying device includes a switching signal generating circuit configured to generate a switching pulse signal for switching a class-D power amplifier from two types of sinusoidal wave generated based on amplitude and phase of a modulated wave to be transmitted. The switching signal generating circuit includes: a sin calculation unit and a cos calculation unit for converting phase information of the two types of sinusoidal wave into a quadrature format; a DA converter for converting the quadrature-format phase information; a first filter for removing an aliasing component from the analogue signal; an analogue quadrature modulator for generating a sinusoidal wave from the analogue signals by using a local signal; a second filter for allowing a radio frequency and a component in the vicinity thereof to pass therethrough; and a comparator for converting the sinusoidal wave into a switching pulse signal by comparison with a reference voltage.