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公开(公告)号：US20150235341A1
公开(公告)日：2015-08-20
申请号：US14182976
申请日：2014-02-18
Applicant: QUALCOMM Incorporated
Inventor： Chunhui Mei , Vineet Goel , Donghyun Kim
CPC classification number: G06T1/60 , G06T1/20 , G06T15/005 , G06T15/80
Abstract: A graphics processing unit (GPU) may allocate a shared data channel in on-chip graphics memory of the GPU that is shared by at least two stages of a graphics processing pipeline. Shader units in the GPU may execute the at least two stages of the graphics processing pipeline. The GPU may store, in the shared data channel in on-chip graphics memory, data produced by each of the at least two stages of the graphics processing pipeline executing on the shader units.
Abstract translation: 图形处理单元（GPU）可以在图形处理流水线的至少两个阶段共享的GPU的片上图形存储器中分配共享数据信道。 GPU中的着色器单元可以执行图形处理流水线的至少两个阶段。 GPU可以在片上图形存储器的共享数据通道中存储在着色器单元上执行的图形处理流水线的至少两个阶段中的每一个生成的数据。
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公开(公告)号：US20130265308A1
公开(公告)日：2013-10-10
申请号：US13830075
申请日：2013-03-14
Applicant: QUALCOMM INCORPORATED
Inventor： Vineet Goel , Andrew E. Gruber , Donghyun Kim
IPC: G06T15/80
Abstract: Aspects of this disclosure relate to a process for rendering graphics that includes performing, with a hardware unit of a graphics processing unit (GPU) designated for vertex shading, a vertex shading operation to shade input vertices so as to output vertex shaded vertices, wherein the hardware unit adheres to an interface that receives a single vertex as an input and generates a single vertex as an output. The process also includes performing, with the hardware unit of the GPU designated for vertex shading, a hull shading operation to generate one or more control points based on one or more of the vertex shaded vertices, wherein the one or more hull shading operations operate on at least one of the one or more vertex shaded vertices to output the one or more control points.
Abstract translation: 本公开的方面涉及用于渲染图形的处理，其包括使用指定为顶点着色的图形处理单元（GPU）的硬件单元执行顶点着色操作以遮蔽输入顶点以输出顶点着色顶点，其中， 硬件单元遵循接收单个顶点作为输入并生成单个顶点作为输出的接口。 该过程还包括使用指定用于顶点着色的GPU的硬件单元执行船体着色操作，以基于顶点着色顶点中的一个或多个生成一个或多个控制点，其中所述一个或多个船体着色操作操作 所述一个或多个顶点着色顶点中的至少一个以输出所述一个或多个控制点。
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公开(公告)号：US10096147B2
公开(公告)日：2018-10-09
申请号：US15066584
申请日：2016-03-10
Applicant: QUALCOMM Incorporated
Inventor： Vineet Goel , Ruijin Wu , Young In Yeo
Abstract: In an example, a method for rendering a 3-D scene of graphical data into a 2-D scene may include dividing 2-D space used to represent the 3-D scene from a viewpoint into a plurality of tiles. The 3-D scene may include a plurality of primitives. The method may include generating visibility information for a first tile of the plurality of tiles. The method may include modifying the visibility information for the first tile to generate modified visibility information for the first tile. The method may include generating the 2-D scene using the modified visibility information for the first tile.
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公开(公告)号：US20170249771A1
公开(公告)日：2017-08-31
申请号：US15054717
申请日：2016-02-26
Applicant: QUALCOMM Incorporated
Inventor： Juraj Obert , Tao Wang , Vineet Goel
CPC classification number: G06T15/005 , G06T15/06 , G06T2200/28 , G06T2210/21
Abstract: A render output unit running on at least one processor may receive a source pixel value to be written to a pixel location in a render target, wherein the source pixel value is associated with a source node in a hierarchical structure. The render output unit may receive a destination pixel value of the pixel location in the render target, wherein the destination pixel value is associated with a destination node in the hierarchical structure. The render output unit may determine a lowest common ancestor node of the source node and the destination node in the hierarchical structure. The render output unit may output a resulting pixel value associated with the lowest common ancestor node of the source node and the destination node to the pixel location in the render target.
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公开(公告)号：US09665975B2
公开(公告)日：2017-05-30
申请号：US14466554
申请日：2014-08-22
Applicant: QUALCOMM Incorporated
Inventor： Vineet Goel , Donghyun Kim , Gang Zhong
CPC classification number: G06T15/83 , G06T15/005
Abstract: This disclosure describes techniques for executing shader programs in a graphics processing unit (GPU). In some examples, the techniques for executing shader programs may include executing, with a shader unit of a graphics processor, a shader program that performs vertex shader processing and that generates multiple output vertices for each input vertex that is received by the shader program. In further examples, the techniques for executing shader programs may include executing a merged vertex/geometry shader program using a non-replicated mode of execution. The non-replicated mode of execution may involve assigning each of a plurality of primitives to one merged vertex/geometry shader program instance per primitive and causing each of the instances to output a plurality of vertices. In additional examples, the techniques for executing shader programs may include techniques for selecting one of a non-replicated mode and a replicated mode for executing a merged vertex/geometry shader program.
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Patent Agency Ranking
公开(公告)号：US09659341B2
公开(公告)日：2017-05-23
申请号：US14749430
申请日：2015-06-24
Applicant: QUALCOMM Incorporated
Inventor： Javier Ignacio Girado , Jay Chunsup Yun , Vineet Goel
CPC classification number: G06T1/20 , G06T7/40 , G06T15/04 , G06T15/80 , G06T2200/28 , G06T2207/20036
Abstract: A texture pipe of a graphics processing unit (GPU) may receive a texture data. The texture pipe may perform a block-based operation on the texture data, wherein the texture data comprises one or more blocks of texels. Shader processors of the GPU may process graphics data concurrently with the texture pipe performing the block-based operation. The texture pipe may output a result of performing the block-based operation on the one or more texture data.
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公开(公告)号：US09305397B2
公开(公告)日：2016-04-05
申请号：US13659675
申请日：2012-10-24
Applicant: QUALCOMM Incorporated
Inventor： Usame Ceylan , Vineet Goel
IPC: G06T17/20
CPC classification number: G06T17/20
Abstract: Systems and methods for a tessellation are described. These systems and methods may divide the domain into a plurality of portions, including a first portion. The systems and methods may also determine coordinates for vertices for a first set of shapes that reside within the first portion, wherein each shape of the first set of shapes includes at least one vertex on a first edge of the first portion. After determining coordinates for the vertices for the first set of shapes, the systems and methods may determine coordinates for vertices for a second set of shapes that reside within the first portion. Each shape of the second set of shapes shares at least one vertex with at least one shape of the first set of shapes and none of the shapes of the second set of shapes includes a vertex on the first edge of the first portion.
Abstract translation: 描述了细分的系统和方法。 这些系统和方法可以将域划分成多个部分，包括第一部分。 系统和方法还可以确定驻留在第一部分内的第一组形状的顶点的坐标，其中第一组形状的每个形状包括在第一部分的第一边缘上的至少一个顶点。 在确定第一组形状的顶点的坐标之后，系统和方法可以确定位于第一部分内的第二组形状的顶点的坐标。 第二组形状的每个形状与至少一个具有第一组形状的形状的至少一个顶点共享，并且第二组形状的形状的一个形状都不包括在第一部分的第一边缘上的顶点。
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公开(公告)号：US09299123B2
公开(公告)日：2016-03-29
申请号：US14160324
申请日：2014-01-21
Applicant: QUALCOMM Incorporated
Inventor： Vineet Goel , Andrew Evan Gruber
CPC classification number: G06T1/20 , G06T1/60 , G06T15/005
Abstract: A graphics processing unit (GPU) includes an indexed streamout buffer. The indexed streamout buffer is configured to: receive vertex data of a primitive, and determine if any entries in a reuse table of the indexed streamout buffer reference the vertex data. Responsive to determining that an entry of in the reuse table references the vertex data, the buffer is further configured to: generate an index that references the vertex data, store the index in the buffer, and store a reference to the index in the reuse table. Responsive to determining that an entry does not reference the vertex data, the indexed streamout buffer is configured to: store the vertex data in the buffer, generate an index that references the vertex data, store the index in the buffer, and store a reference to the index in the reuse table.
Abstract translation: 图形处理单元（GPU）包括索引流出缓冲器。 索引的流出缓冲器被配置为：接收原语的顶点数据，并且确定索引的流出缓冲器的重用表中的任何条目是否引用顶点数据。 响应于确定所述重用表中的条目引用所述顶点数据，所述缓冲器还被配置为：生成引用所述顶点数据的索引，将所述索引存储在所述缓冲器中，并且存储对所述重用表中的所述索引的引用 。 响应于确定条目不引用顶点数据，索引流出缓冲器被配置为：将顶点数据存储在缓冲器中，生成引用顶点数据的索引，将索引存储在缓冲器中，并存储引用 重用表中的索引。
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公开(公告)号：US20150379676A1
公开(公告)日：2015-12-31
申请号：US14749430
申请日：2015-06-24
Applicant: QUALCOMM Incorporated
Inventor： Javier Ignacio Girado , Jay Chunsup Yun , Vineet Goel
CPC classification number: G06T1/20 , G06T7/40 , G06T15/04 , G06T15/80 , G06T2200/28 , G06T2207/20036
Abstract: A texture pipe of a graphics processing unit (GPU) may receive a texture data. The texture pipe may perform a block-based operation on the texture data, wherein the texture data comprises one or more blocks of texels. Shader processors of the GPU may process graphics data concurrently with the texture pipe performing the block-based operation. The texture pipe may output a result of performing the block-based operation on the one or more texture data.
Abstract translation: 图形处理单元（GPU）的纹理管道可以接收纹理数据。 纹理管可以对纹理数据执行基于块的操作，其中纹理数据包括一个或多个纹理块。 GPU的着色器处理器可以与执行基于块的操作的纹理管线同时处理图形数据。 纹理管道可以输出对一个或多个纹理数据执行基于块的操作的结果。
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公开(公告)号：US20150235340A1
公开(公告)日：2015-08-20
申请号：US14454394
申请日：2014-08-07
Applicant: QUALCOMM Incorporated
Inventor： Ouns Mouri , Vineet Goel , Tao Wang
CPC classification number: G06T1/20 , G06T11/40 , G06T17/10 , G09G5/18 , G09G2310/08
Abstract: This disclosure describes a method for performing conservative rasterization in a processor comprising determining vertices of a primitive, defining edges of the primitive by determining a set of edge equations based on the determined vertices, wherein the edge equations are based on an edge shifting parameter plus an offset, determining pixels that touch the edges of the primitive using the determined edge equations, and rasterizing the primitive using the determined pixels.
Abstract translation: 本公开描述了一种用于在处理器中执行保守光栅化的方法，包括通过基于所确定的顶点确定一组边缘方程来确定原语的边缘来定义基元的边缘，其中边缘方程基于边缘移位参数加上 使用所确定的边缘方程来确定触摸图元的边缘的像素，以及使用所确定的像素来对原图进行光栅化。
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