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    METHOD AND APPARATUS FOR COMPUTER MODEL RASTERIZATION
    1.
    发明申请
    METHOD AND APPARATUS FOR COMPUTER MODEL RASTERIZATION 有权

    公开(公告)号：US20230011882A1

    公开(公告)日：2023-01-12

    申请号：US17370782

    申请日：2021-07-08

    申请人： Yan LUO ,  Botao XIAO

    发明人： Yan LUO ,  Botao XIAO

    IPC分类号： G06T15/83 ,  G06T15/50 ,  G06T15/00

    摘要： There is described a method of rasterizing a computer model. One or more non-linear expressions of code are identified in a fragment shader. The one or more non-linear expressions of code are transformed into one or more linear expressions of code. The one or more linear expressions of code are transferred from the fragment shader to a vertex shader. The computer model is then rasterized by executing, on the computer model, code comprised in the vertex shader, including the transferred one or more linear expressions of code.

    Device and method for estimating a glossy part of radiation
    3.
    发明授权
    Device and method for estimating a glossy part of radiation 有权

    公开(公告)号：US10607404B2

    公开(公告)日：2020-03-31

    申请号：US15044083

    申请日：2016-02-15

    申请人： THOMSON LICENSING

    发明人： Pascal Lecocq ,  Gael Sourimant ,  Jean-Eudes Marvie

    IPC分类号： G06T15/83 ,  G06T15/50 ,  G06T1/20 ,  G06T15/55

    摘要： The present invention relates to a glossy part of radiation is estimated coming from a surface illuminated by area light source(s) having source surface(s) (A) bounded by edge curves, by determining integrand function(s) representative of that glossy part. The latter corresponding to an integration of the integrand function along the edge curves. In this respect, the integrand function(s) is/are approximated by means of peak-shape function(s) having a known antiderivative over the edge curves, and the glossy part is computed from analytical expressions associated with integrations of the peak-shape function(s) along the edge curves. Such invention can offer efficient and accurate computation for specular part of reflection as well as glossy transmission, and is notably relevant to real-time rendering.

    SHADER BINDING MANAGEMENT IN RAY TRACING
    4.
    发明申请
    SHADER BINDING MANAGEMENT IN RAY TRACING 审中-公开

    公开(公告)号：US20190311531A1

    公开(公告)日：2019-10-10

    申请号：US16376943

    申请日：2019-04-05

    申请人： NVIDIA Corporation

    发明人： Martin Stich ,  Ignacio Llamas ,  Steven Parker

    IPC分类号： G06T15/83 ,  G06T15/06 ,  G06T15/00 ,  G06F9/54

    摘要： In various examples, shader bindings may be recorded in a shader binding table that includes shader records. Geometry of a 3D scene may be instantiated using object instances, and each may be associated with a respective set of the shader records using a location identifier of the set of shader records in memory. The set of shader records may represent shader bindings for an object instance under various predefined conditions. One or more of these predefined conditions may be implicit in the way the shader records are arranged in memory (e.g., indexed by ray type, by sub-geometry, etc.). For example, a section selector value (e.g., a section index) may be computed to locate and select a shader record based at least in part on a result of a ray tracing query (e.g., what sub-geometry was hit, what ray type was traced, etc.).

    SHADER PROGRAM EXECUTION TECHNIQUES FOR USE IN GRAPHICS PROCESSING
    6.
    发明申请
    SHADER PROGRAM EXECUTION TECHNIQUES FOR USE IN GRAPHICS PROCESSING 有权
    用于图形处理的较差程序执行技术

    公开(公告)号：US20160055667A1

    公开(公告)日：2016-02-25

    申请号：US14466554

    申请日：2014-08-22

    申请人： QUALCOMM Incorporated

    发明人： Vineet Goel ,  Donghyun Kim ,  Gang Zhong

    IPC分类号： G06T15/83 ,  G06T15/00

    CPC分类号： G06T15/83 ,  G06T15/005

    摘要： This disclosure describes techniques for executing shader programs in a graphics processing unit (GPU). In some examples, the techniques for executing shader programs may include executing, with a shader unit of a graphics processor, a shader program that performs vertex shader processing and that generates multiple output vertices for each input vertex that is received by the shader program. In further examples, the techniques for executing shader programs may include executing a merged vertex/geometry shader program using a non-replicated mode of execution. The non-replicated mode of execution may involve assigning each of a plurality of primitives to one merged vertex/geometry shader program instance per primitive and causing each of the instances to output a plurality of vertices. In additional examples, the techniques for executing shader programs may include techniques for selecting one of a non-replicated mode and a replicated mode for executing a merged vertex/geometry shader program.

    摘要翻译： 本公开描述了用于在图形处理单元（GPU）中执行着色器程序的技术。 在一些示例中，用于执行着色器程序的技术可以包括使用图形处理器的着色器单元执行着色器程序，该着色器程序执行顶点着色器处理，并且为着色器程序接收的每个输入顶点生成多个输出顶点。 在另外的示例中，用于执行着色器程序的技术可以包括使用非复制的执行模式来执行合并的顶点/几何着色器程序。 非复制的执行模式可以包括将多个基元中的每一个分配给每个基元的一个合并的顶点/几何着色器程序实例，并使每个实例输出多个顶点。 在附加示例中，用于执行着色器程序的技术可以包括用于选择非复制模式和用于执行合并顶点/几何着色器程序的复制模式之一的技术。

    3-D graphics display system using triangle processor pipeline
    7.
    发明授权
    3-D graphics display system using triangle processor pipeline 失效
    3-D图形显示系统采用三角形处理器管线

    公开(公告)号：US4885703A

    公开(公告)日：1989-12-05

    申请号：US117111

    申请日：1987-11-04

    申请人： Michael F. Deering

    发明人： Michael F. Deering

    IPC分类号： G06T15/83

    CPC分类号： G06T15/83

    摘要： A graphic processing system for representing three-dimensional objects on a monitor which uses a pipeline of polygon processors coupled in series. The three-dimensional objects are converted into a group of two-dimensional polygons. These polygons are then sorted to put them in scan line order, with each polygon having its position determined by the first scan line on which it appears. Before each scan line is processed, the descriptions of the polygons beginning on that scan line are sent into a pipeline of polygon processors. Each polygon processor accepts one of the polygon descriptions and stores it for comparison to the pixels of that scan line which are subsequently sent along the polygon processor pipeline. For each new scan line, polygons which are no longer covered are eliminated and new polygons are entered into the pipe. After each scan line is processed, the pixels can be sent directly to the CRT or can be stored in a frame buffer for later accessing. Two polygon processor pipelines can be arranged in parallel to process two halves of a display screen, with one pipeline being loaded while the other is processing. A frame buffer and frame buffer controller are provided for overflow conditions where two passes through the polygon pipeline are needed. A unique clipping algorithm forms a guardband space around a viewing space and clips only polygons intersecting both shells. Extra areas processed are simply not displayed.

    摘要翻译： 一种用于在监视器上表示三维物体的图形处理系统，该监视器使用串联耦合的多边形处理器的流水线。 三维物体被转换为一组二维多边形。 然后对这些多边形进行排序以将它们放置成扫描线顺序，每个多边形的位置由其出现的第一条扫描线确定。 在每个扫描线被处理之前，从该扫描线开始的多边形的描述被发送到多边形处理器的流水线。 每个多边形处理器接受多边形描述中的一个，并将其存储为与沿多边形处理器流水线发送的该扫描线的像素进行比较。 对于每个新的扫描线，不再覆盖的多边形被消除，并且新的多边形被输入到管道中。 在每个扫描线被处理之后，像素可以被直接发送到CRT，或者可以存储在帧缓冲器中以备以后访问。 两个多边形处理器管线可以并行布置，以处理显示屏幕的两个半部分，一个管道被加载，另一个处理。 提供帧缓冲器和帧缓冲器控制器用于需要两个通过多边形管道的溢出条件。 唯一的剪切算法在观看空间周围形成一个保护带空间，并且仅剪切与两个外壳相交的多边形。 处理的额外区域根本不显示。

    Snapshot arbitration techniques for memory requests
    8.
    发明授权
    Snapshot arbitration techniques for memory requests 有权

    公开(公告)号：US11842436B2

    公开(公告)日：2023-12-12

    申请号：US17816632

    申请日：2022-08-01

    申请人： Apple Inc.

    发明人： Winnie W. Yeung ,  Leela Kishore Kothamasu ,  Zelin Zhang ,  Guanlan Xu ,  Eddie M. Robinson

    IPC分类号： G06F13/362 ,  G06T15/83 ,  G06T15/04 ,  G06T15/00 ,  G06F13/16

    CPC分类号： G06T15/83 ,  G06F13/1668 ,  G06F13/3625 ,  G06T15/005 ,  G06T15/04

    摘要： Techniques are disclosed relating to arbitration for computer memory resources. In some embodiments, an apparatus includes queue circuitry that implements multiple queues configured to queue requests to access a memory bus. Control circuitry may, in response to detecting a first threshold condition associated with the queue circuitry, generate a first snapshot that indicates numbers of requests in respective queues of the multiple queues at a first time. The control circuitry may generate a second snapshot that indicates numbers of requests in respective queues of the multiple queues at a second time that is subsequent to the first time. The control circuitry may arbitrate between requests from the multiple queues to select requests to access the memory bus, where the arbitration is based on snapshots to which requests from the multiple queues belong. Disclosed techniques may approximate age-based scheduling while reducing area and power consumption.