公开(公告)号：US11895321B2

公开(公告)日：2024-02-06

申请号：US17704689

申请日：2022-03-25

Applicant: QUALCOMM Incorporated

Inventor： Yan Zhang ,  Zhi Zhang ,  Vadim Seregin ,  Marta Karczewicz ,  Chun-Chi Chen

IPC: H04N19/52 ,  H04N19/70 ,  H04N19/105 ,  H04N19/55 ,  H04N19/176

CPC classification number: H04N19/52 ,  H04N19/105 ,  H04N19/55 ,  H04N19/70 ,  H04N19/176

Abstract: An example device includes memory configured to store the video data and one or more processors implemented in circuitry and communicatively coupled to the memory. The one or more processors are configured to determine at least one of a temporal candidate or a history-based candidate and determine at least one non-adjacent candidate, wherein the at least one non-adjacent candidate is from a unit that is not adjacent to a current prediction unit (PU). The one or more processors are configured to determine an advanced motion vector predictor (AMVP) candidate list including the at least one of the temporal candidate or the history-based candidate and the at least one non-adjacent candidate. The at least one non-adjacent candidate is added to the AMVP candidate list after the temporal candidate or before the history-based candidate. The one or more processors are configured to code the current PU based on the AMVP candidate list.

公开(公告)号：US20230328257A1

公开(公告)日：2023-10-12

申请号：US18194013

申请日：2023-03-31

Applicant: QUALCOMM Incorporated

Inventor： Zhi Zhang ,  Han Huang ,  Yao-Jen Chang ,  Chun-Chi Chen ,  Yan Zhang ,  Vadim Seregin ,  Marta Karczewicz

IPC: H04N19/159 ,  H04N19/563 ,  H04N19/52 ,  H04N19/176 ,  H04N19/14

CPC classification number: H04N19/159 ,  H04N19/563 ,  H04N19/52 ,  H04N19/176 ,  H04N19/14

Abstract: A device for decoding video data includes a memory configured to store video data; and one or more processors implemented in circuitry and configured to: determine that a boundary block of a picture of the video data is bi-directional inter-predicted using a first motion vector and a second motion vector, the boundary block having an edge that touches an edge of the picture; decode the picture, including decoding the boundary block; form a first intermediate padding block using the first motion vector; form a second intermediate padding block using the second motion vector; form a padding block using the first intermediate padding block and the second intermediate padding block; and assign padding values of the padding block to a padding region of the picture neighboring the boundary block on an opposite side of the edge of the picture.

公开(公告)号：US20230094825A1

公开(公告)日：2023-03-30

申请号：US17929122

申请日：2022-09-01

Applicant: QUALCOMM Incorporated

Inventor： Yan Zhang ,  Bappaditya Ray ,  Vadim Seregin ,  Marta Karczewicz

IPC: H04N19/137 ,  H04N19/88 ,  H04N19/176

Abstract: A video decoder may be configured to construct motion vector candidates using possible sign values, respective magnitudes of motion vector difference components, and a motion vector predictor for a block of video data, wherein the possible sign values include a positive sign value and a negative sign value, sort the motion vector candidates based on a cost for each of the motion vector candidates to create a sorted list, determine a respective motion vector difference sign for each motion vector difference coordinate based on a motion vector sign predictor index and the sorted list, and decode the block of video data using the respective magnitudes of motion vector difference coordinates and the respective motion vector difference sign for each motion vector difference component.

公开(公告)号：US20230007238A1

公开(公告)日：2023-01-05

申请号：US17809167

申请日：2022-06-27

Applicant: QUALCOMM Incorporated

Inventor： Chun-Chi Chen ,  Han Huang ,  Cheng-Teh Hsieh ,  Wei-Jung Chien ,  Zhi Zhang ,  Yao-Jen Chang ,  Yan Zhang ,  Vadim Seregin ,  Marta Karczewicz

IPC: H04N19/105 ,  H04N19/132 ,  H04N19/137 ,  H04N19/176

Abstract: A device for decoding video data includes a memory configured to store video data; and one or more processors implemented in circuitry and configured to: determine a deterministic bounding box from which to retrieve reference samples of reference pictures of video data for performing decoder-side motion vector derivation (DMVD) for a current block of the video data; derive a motion vector for the current block according to DMVD using the reference samples within the deterministic bounding box; form a prediction block using the motion vector; and decode the current block using the prediction block.

公开(公告)号：US11533512B2

公开(公告)日：2022-12-20

申请号：US17225801

申请日：2021-04-08

Applicant: QUALCOMM Incorporated

Inventor： Dmytro Rusanovskyy ,  Adarsh Krishnan Ramasubramonian ,  Yan Zhang ,  Marta Karczewicz

IPC: H04N19/70 ,  H04N19/172 ,  H04N19/169

Abstract: An example device for processing video data includes memory configured to store the video data and one or more processors implemented in circuitry and coupled to the memory. The one or more processors are configured to parse a first parameter set, the first parameter set being signaled in a bitstream data once per sequence of a group of encoded pictures. The one or more processors are configured to parse one or more dynamic range adjustment (DRA) syntax elements in a second parameter set, the second parameter set being signaled in the bitstream and being related to at least one picture in the group of encoded pictures, wherein the parsing of the one or more DRA syntax elements is not dependent on any syntax element of the first parameter set, and process the at least one picture based on the first parameter set and the second parameter set.

公开(公告)号：US20220352878A1

公开(公告)日：2022-11-03

申请号：US17238173

申请日：2021-04-22

Applicant: Qualcomm Incorporated

Inventor： Yan Zhang ,  Yunliang Zhu ,  Yiwu Tang

IPC: H03K5/00 ,  H03B19/14 ,  H03B19/10 ,  H04B1/04 ,  H04L27/36

Abstract: This disclosure describes apparatuses, methods, and techniques for implementing a multimode frequency multiplier. In example implementations, an apparatus for generating a frequency includes a multimode frequency multiplier. The multimode frequency multiplier includes a multiphase generator and a reconfigurable frequency multiplier. The multiphase generator is configured to produce a first signal including multiple phase components and having a first frequency. The reconfigurable frequency multiplier is coupled in series with the multiphase generator. The reconfigurable frequency multiplier is configured to produce a second signal based on the first signal and having a second frequency that is a multiple of the first frequency.

公开(公告)号：US20220312030A1

公开(公告)日：2022-09-29

申请号：US17704689

申请日：2022-03-25

Applicant: QUALCOMM Incorporated

Inventor： Yan Zhang ,  Zhi Zhang ,  Vadim Seregin ,  Marta Karczewicz ,  Chun-Chi Chen

IPC: H04N19/52 ,  H04N19/105 ,  H04N19/70

Abstract: An example device includes memory configured to store the video data and one or more processors implemented in circuitry and communicatively coupled to the memory. The one or more processors are configured to determine at least one of a temporal candidate or a history-based candidate and determine at least one non-adjacent candidate, wherein the at least one non-adjacent candidate is from a unit that is not adjacent to a current prediction unit (PU). The one or more processors are configured to determine an advanced motion vector predictor (AMVP) candidate list including the at least one of the temporal candidate or the history-based candidate and the at least one non-adjacent candidate. The at least one non-adjacent candidate is added to the AMVP candidate list after the temporal candidate or before the history-based candidate. The one or more processors are configured to code the current PU based on the AMVP candidate list.

公开(公告)号：US11317111B2

公开(公告)日：2022-04-26

申请号：US17033659

申请日：2020-09-25

Applicant: QUALCOMM Incorporated

Inventor： Dmytro Rusanovskyy ,  Marta Karczewicz ,  Yan Zhang

IPC: H04N19/513 ,  H04N19/176 ,  H04N19/186 ,  H04N19/103 ,  H04N19/132 ,  H04N19/139

Abstract: Systems and techniques for video coding and compression are described herein. Some examples include affine coding modes for video coding and compression. One example is an apparatus for coding video data that includes a memory and a processor or processors coupled to the memory. The processor(s) are configured to obtain a current coding block from the video data, determine control data for the current coding block, and determine one or more affine motion vector clipping parameters from the control data. The processor(s) are further configured to select a sample of the current coding block, determine an affine motion vector for the sample of the current coding block, and clip the affine motion vector using the one or more affine motion vector clipping parameters to generate a clipped affine motion vector.

公开(公告)号：US20210211672A1

公开(公告)日：2021-07-08

申请号：US17142157

申请日：2021-01-05

Applicant: QUALCOMM Incorporated

Inventor： Dmytro Rusanovskyy ,  Yan Zhang ,  Marta Karczewicz

IPC: H04N19/13 ,  H04N19/176 ,  H04N19/42 ,  H04N19/91

Abstract: An example device for coding video data includes a memory configured to store video data; and one or more processors implemented in circuitry and configured to: determine a size of a dimension of a current block of the video data; calculate a context for entropy coding a last significant coefficient coordinate along the dimension, wherein to calculate the context, the one or more processors are configured to: calculate a context shift value according to ((log 2TrafoSize+1)>>2) >’ represents a bitwise right shift operator, and ‘

公开(公告)号：US20250119565A1

公开(公告)日：2025-04-10

申请号：US18882254

申请日：2024-09-11

Applicant: QUALCOMM Incorporated

Inventor： Yan Zhang ,  Vadim Seregin ,  Hongtao Wang ,  Zhi Zhang ,  Chun-Chi Chen ,  Han Huang ,  Marta Karczewicz

IPC: H04N19/44 ,  H04N19/105 ,  H04N19/176

Abstract: Example devices, methods, and computer-readable media for decoding video data are described. An example method includes determining to decode a current block of the video data using a merge mode. The example method includes generating a first merge list for the current block, wherein generating the first merge list comprises applying template matching to candidates of the first merge list. The example method includes generating, based on the first merge list, a second merge list. The example method includes decoding the current block using the merge mode and based on the first merge list or the second merge list.