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公开(公告)号：US20230361761A1
公开(公告)日：2023-11-09
申请号：US18143854
申请日：2023-05-05
申请人： Paragraf Limited
发明人： Ivor GUINEY , Thomas James BADCOCK , Robert WALLIS
CPC分类号： H03K5/00006 , H03B19/14
摘要： According to a first aspect of the disclosure, an integrated frequency multiplier circuit is provided. The circuit comprises a substrate, a strip of graphene, first and second electrode, a dielectric layer, a frequency input electrode, and a frequency output electrode. The strip of graphene has a uniform width provided on the substrate, the strip having a width x and a length y extending from a first end to a second end. The first and second electrodes are provided in electrical contact with the strip of graphene at the first and second ends of the strip of graphene respectively. The dielectric layer is provided on the strip of graphene, wherein the dielectric layer is provided across the width x of the strip of graphene. The frequency input electrode is formed on the dielectric layer, wherein the frequency input electrode is provided across the width x of the strip of graphene. The frequency input electrode is provided over the strip of graphene at a location closer to the first end of the strip of graphene than the second end. The frequency output electrode is provided in electrical contact with the strip of graphene at a location along the length of the strip of graphene between the second electrode and the frequency input electrode, spaced apart from the second electrode.
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公开(公告)号：US20220103127A1
公开(公告)日：2022-03-31
申请号：US17550107
申请日：2021-12-14
发明人： Mihai Banu , Yiping Feng
IPC分类号： H03D7/14 , H03L7/081 , H03L7/093 , H03L7/099 , H03F3/45 , H03K5/00 , H03C3/09 , H03B19/14 , H03L7/185 , H03L7/085
摘要： An electronic circuit including: a differential multiplier circuit with a first differential input and a second differential input and a differential output; and a phase locked loop (PLL) circuit including: (1) a balanced differential mixer circuit with a first differential input electrically connected to the differential output of the differential multiplier circuit, a second differential input, and an output; (2) a loop filter having an output and an input electrically connected to the output of the balanced differential mixer circuit; and (3) a voltage controlled oscillator (VCO) circuit having an input electrically connected to the output of the loop filter and with an output electrically feeding back to the second differential input of the balanced differential mixer circuit.
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公开(公告)号：US10944386B1
公开(公告)日：2021-03-09
申请号：US16928218
申请日：2020-07-14
摘要： Certain aspects of the present disclosure generally relate to techniques and apparatus for doubling the frequency of a signal. For example, certain aspects are directed to a phase frequency detector (PFD)-based rising-edge-delay-only frequency doubling circuit. One example frequency doubler circuit generally includes a first delay stage, a second delay stage, a first PFD, a first rising-edge-only adjustable delay cell, a second PFD, a second rising-edge-only adjustable delay cell a logic gate, and a comparator configured to compare a direct-current (DC) voltage value of an output of the logic gate with a reference voltage and control the first and second rising-edge-only adjustable delay cells based on the comparison.
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公开(公告)号：US10581379B2
公开(公告)日：2020-03-03
申请号：US16437001
申请日：2019-06-11
摘要： An integrated circuit includes first and second coils, a first pad connected to the first coil and to a resonator, a second pad connected to the second coil and to the resonator, and first and second output terminals. The first pad is arranged to provide signals between the resonator and the first coil. The second pad is arranged to provide signals between the resonator and the second coil. A distance between the first pad and the first coil is less than a distance between the first coil and the first output terminal and a distance between the first coil and the second output terminal. A distance between the second pad and the second coil is less than a distance between the second coil and the first output terminal and a distance between the second coil and the second output terminal.
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公开(公告)号：US20200067458A1
公开(公告)日：2020-02-27
申请号：US16108972
申请日：2018-08-22
发明人： Petr Senfluk , Petr Gross
摘要： A circuit that receives AC power for rectification and analog DC control signals for processing. Two voltages may be noted. A first voltage may be between a supply ground and an internal device ground of a rectifier. A second voltage may be between a terminal of an input control signal source and the internal device ground. To get a control signal value, one may need a differential of those two voltages that can be accomplished with an operational amplifier configured as differential amplifier. A range of an input control signal may be from zero to a particular magnitude of voltage. A reasonably priced operational amplifier might not have an ability provide an output to zero. However, a linearized transistor output stage, having an output that can go to zero, may be connected to an output of the operational amplifier so as to effectively provide an output that goes to zero.
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公开(公告)号：US10418942B2
公开(公告)日：2019-09-17
申请号：US15171373
申请日：2016-06-02
申请人： Intel IP Corporation
发明人： Igal Yehuda Kushnir , Gil Horovitz , Ronen Kronfeld , Sarit Zur
摘要： Embodiments of a reference path circuit and communication device are generally described herein. The reference path circuit may include an injection locked multiplier (ILM) and a group of one or more buffer amplifiers. The ILM may receive a sinusoidal reference signal from a reference oscillator at a reference frequency. The ILM may generate a sinusoidal ILM output signal at an ILM output frequency that is based on an integer multiple of the reference frequency. The integer multiple of the reference frequency may be within a locking range of the ILM that may be based on a resonant frequency of the ILM. The group of one or more buffer amplifiers may generate an output clock signal for input to the frequency synthesizer. The output clock signal may be based on a sign function of the ILM output signal.
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公开(公告)号：US20170149438A1
公开(公告)日：2017-05-25
申请号：US15425597
申请日：2017-02-06
发明人： Quan Xue , Haifeng Zhou , Kam Man Shum
IPC分类号： H03L7/099 , H01L49/02 , H03B19/14 , H01L21/768 , H01L29/66 , H01L21/8234 , H01L27/06
CPC分类号： H03L7/099 , H01L21/768 , H01L21/76895 , H01L21/823475 , H01L23/645 , H01L27/0207 , H01L27/0641 , H01L27/088 , H01L28/10 , H01L29/0696 , H01L29/4238 , H01L29/78 , H03B5/1212 , H03B5/1228 , H03B19/14 , H03D3/24
摘要： Transistors can be used for a variety of electronic-based applications. Therefore, transistor efficiency and performance is of importance. An apparatus is presented herein to increase the locking range of transistors by leveraging cross-coupled injection transistors in conjunction with symmetry injection transistors. The transistor efficiency can also be increase by reducing a parasitic capacitance associated with the components of the transistor.
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8.发明授权公开(公告)号：US09577575B2
公开(公告)日：2017-02-21
申请号：US14966294
申请日：2015-12-11
发明人： Kang Yoon Lee , Sang Yun Kim , Young Jun Park , Dong Soo Lee
CPC分类号： H03B19/14 , H03B2200/007 , H03B2200/0074 , H03K3/0315 , H03K3/0322
摘要： An injection locked frequency divider is disclosed. The injection-locked frequency divider includes a sub-harmonic injection-locked oscillator, a reference clock divider, a counter, and a variable load resistor control unit. The sub-harmonic injection-locked oscillator has variable load resistors that are adjusted in response to a resistance adjustment signal, and, when oscillation frequency determined based on the magnitudes of the variable load resistors is a sub-harmonic of an injection signal, outputs signals having the oscillation frequency as divided output signals. The reference clock divider generates a count-enable signal from a reference clock signal according to a reference division ratio. The counter generates divided output count signals based on the divided output signals in response to the count-enable signal. The variable load resistor control unit compares target count values, determined based on the target frequencies of the divided output signals, with the divided output count signals, and outputs the resistance adjustment signal.
摘要翻译： 公开了一种注入锁定分频器。 注入锁定分频器包括子谐波注入锁定振荡器，参考时钟分频器，计数器和可变负载电阻控制单元。 子谐波注入锁定振荡器具有响应于电阻调节信号而调节的可变负载电阻器，并且当基于可变负载电阻器的幅度确定的振荡频率是喷射信号的次谐波时，输出信号 具有作为分频输出信号的振荡频率。 参考时钟分频器根据参考分频比从参考时钟信号产生计数使能信号。 计数器响应于计数使能信号，基于划分的输出信号产生分割的输出计数信号。 可变负载电阻控制单元将根据划分的输出信号的目标频率确定的目标计数值与划分的输出计数信号进行比较，并输出电阻调节信号。
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公开(公告)号：US09515638B2
公开(公告)日：2016-12-06
申请号：US14617468
申请日：2015-02-09
发明人： Wooram Lee , Alberto Valdes Garcia
CPC分类号： H03K5/00006 , H03B19/14
摘要： Methods for frequency multiplying include receiving a signal having an input frequency at a frequency multiplier comprising a pair of transistors; and selecting a harmonic in the signal by connecting the transistors to a common impedance through a respective collector impedance, wherein an output frequency at the harmonic between the collector impedances and the common impedance is an even integer multiple of an input frequency.
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10.发明授权Apparatus and method for generating quadrupled reference clock from single ended crystal oscillator 有权从单端晶体振荡器产生四倍参考时钟的装置和方法公开(公告)号：US09490784B2
公开(公告)日：2016-11-08
申请号：US14640672
申请日：2015-03-06
CPC分类号： H03K5/00006 , H03B19/10 , H03B19/14 , H03K5/1565
摘要： A method, an apparatus, and a computer program product are provided. The apparatus outputs a sinusoidal signal according to a first clock frequency, generates, a first digital signal having a 25% duty cycle based on the sinusoidal signal, generates a second digital signal having a 25% duty cycle based on the sinusoidal signal, combines the first digital signal and the second digital signal to generate a combined digital signal having a 50% duty cycle and a second clock frequency that is double the first clock frequency, and doubles the second clock frequency of the combined digital signal to generate an output signal having a third clock frequency that is quadruple the first clock frequency. The apparatus further generates a first control voltage and a second control voltage for the first buffer and a third control voltage for the second buffer based on the output signal.
摘要翻译： 提供了一种方法，装置和计算机程序产品。 该装置根据第一时钟频率输出正弦信号，产生基于正弦信号的具有25％占空比的第一数字信号，产生基于正弦信号具有25％占空比的第二数字信号， 第一数字信号和第二数字信号，以产生具有50％占空比和第二时钟频率的组合数字信号，该第二时钟频率是第一时钟频率的两倍，并且使组合数字信号的第二时钟频率加倍，以产生具有 第三个时钟频率是第一个时钟频率的四倍。 该装置还基于输出信号产生用于第一缓冲器的第一控制电压和第二控制电压以及第二缓冲器的第三控制电压。
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