公开(公告)号：US07117405B2

公开(公告)日：2006-10-03

申请号：US10249648

申请日：2003-04-28

申请人： Ramon S. Co ,  Tat Leung Lai ,  David Da-Wei Sun

发明人： Ramon S. Co ,  Tat Leung Lai ,  David Da-Wei Sun

IPC分类号： G11C29/00 ,  G06F11/00

CPC分类号： G11C29/48 ,  G11C16/04

摘要： An extender card is plugged into a memory module socket on a personal computer (PC) motherboard. The extender card has a test socket that receives a memory module under test. The extender card has an intercepting EEPROM chip that receives device-select lines from the motherboard. One of the device-select lines from the motherboard to a module EEPROM chip on the memory module is blocked by the extender card and altered so that the intercepting EEPROM chip is read by the motherboard rather than the module EEPROM chip. A memory configuration is read from the intercepting EEPROM chip. The memory module is tested by the motherboard using the configuration from the intercepting EEPROM chip on the extender card. The module EEPROM chip is then programmed with the configuration by altering the intercepted device-select address to select the module EEPROM chip and not the intercepting EEPROM chip.

摘要翻译： 扩展卡插入个人计算机（PC）主板上的内存模块插槽。 扩展卡具有接收被测内存模块的测试插槽。 扩展卡具有从主板接收设备选择线的截取EEPROM芯片。 从主板到存储器模块上的模块EEPROM芯片的一个设备选择线被扩展卡阻挡，并被改变，从而拦截EEPROM芯片被主板而不是模块EEPROM芯片读取。 从截取的EEPROM芯片读取存储器配置。 内存模块由主板使用扩展卡上拦截EEPROM芯片的配置进行测试。 然后通过更改截取的器件选择地址来选择模块EEPROM芯片，而不是拦截EEPROM芯片，将模块EEPROM芯片编程为配置。

公开(公告)号：US08493745B2

公开(公告)日：2013-07-23

申请号：US13269526

申请日：2011-10-07

申请人： Ramon S. Co

发明人： Ramon S. Co

IPC分类号： H05K7/00

CPC分类号： G06F1/185

摘要： A low-profile personal computer (PC) motherboard has memory modules mounted to an edge of the motherboard rather than mounted perpendicular using standard memory module sockets. The PC motherboard has a lower profile since memory module sockets are removed from the top surface of the PC motherboard. Expansion card sockets are also removed by integrating expansion functions into chips on the PC motherboard, or using an edge-mounted connector to the expansion card or to an external peripheral. Motherboard metal contacts are formed on an extended plug region near the edge of the PC motherboard. A first opening or slot of an edge connector fits over the motherboard metal contacts, while a second opening or slot of the edge connector fits over metal contacts on a standard memory module. The memory module and the PC motherboard each have printed-circuit boards (PCBs) that are in the same plane, thus reducing the overall height.

摘要翻译： 一个低调的个人计算机（PC）主板具有安装在主板边缘的内存模块，而不是使用标准内存模块插槽垂直安装。 PC主板具有较低的外形，因为内存模块插座从PC主板的顶面移除。 扩展卡插槽也可以通过将扩展功能集成到PC主板上的芯片中，或者使用边缘连接器连接到扩展卡或外部外围设备。 主板金属触点形成在靠近PC主板边缘的扩展插头区域上。 边缘连接器的第一开口或槽口装配在母板金属触点上，而边缘连接器的第二开口或槽适合标准存储器模块上的金属触点。 存储器模块和PC主板各自具有位于同一平面中的印刷电路板（PCB），从而降低了整体高度。

公开(公告)号：US07797583B2

公开(公告)日：2010-09-14

申请号：US12036985

申请日：2008-02-25

申请人： Ramon S. Co

发明人： Ramon S. Co

IPC分类号： G06F11/00

CPC分类号： G06F11/2733 ,  G01R31/31723 ,  G01R31/31905 ,  G11C5/04 ,  G11C29/56 ,  G11C29/56016 ,  G11C2029/5602

摘要： A test adaptor board connects to a personal computer (PC) motherboard that tests a memory module in a test socket. A standard memory module socket is removed from a target DRAM module slot on the component side and the test adaptor board connects to the target DRAM module slot on the reverse (solder) side of the motherboard. The target DRAM module slot is a middle slot, such as the second or third of four DRAM module slots. The first and fourth DRAM module slots are populated with known good memory modules storing the BIOS at a high address and an operating system image and a test program at a low address. The test program accesses a memory module in the test socket to locate defects. The motherboard does not crash since the BIOS, OS image, and test program are not stored in the memory module under test.

摘要翻译： 测试适配器板连接到测试测试插座中的内存模块的个人计算机（PC）主板。 从组件侧的目标DRAM模块插槽中移除标准内存模块插座，测试适配器板连接到主板背面（焊锡）侧的目标DRAM模块插槽。 目标DRAM模块插槽是中间插槽，例如四个DRAM模块插槽的第二或第三。 第一和第四DRAM模块插槽用已知的良好存储器模块填充存储在高地址处的BIOS，操作系统映像和低地址处的测试程序。 测试程序访问测试套接字中的内存模块来定位缺陷。 主板不会崩溃，因为BIOS，OS映像和测试程序未存储在被测内存模块中。

公开(公告)号：US07474576B2

公开(公告)日：2009-01-06

申请号：US12053261

申请日：2008-03-21

申请人： Ramon S. Co ,  David Sun

发明人： Ramon S. Co ,  David Sun

IPC分类号： G11C29/00

CPC分类号： G11C5/04 ,  G11C29/808 ,  G11C29/88

摘要： A repairing fully-buffered memory module can have memory chips with some defects such as single-bit errors. A repair controller is added to the Advanced Memory Buffer (AMB) on the memory module. The AMB fully buffers memory requests that are sent as serial packets over southbound lanes from a host. Memory-access addresses are extracted from the serial packets by the AMB. The repair controller compares the memory-access addresses to repair addresses and diverts access from defective memory chips to a spare memory for the repair addresses. The repair addresses can be located during testing of the memory module and programmed into a repair address buffer on the AMB. The repair addresses could be first programmed into a serial-presence-detect electrically-erasable programmable read-only memory (SPD-EEPROM) on the memory module, and then copied to the repair address buffer on the AMB during power-up.

摘要翻译： 修复全缓冲存储器模块可以具有存在诸如单位错误等缺陷的存储器芯片。 修复控制器被添加到内存模块的高级内存缓冲区（AMB）中。 AMB完全缓冲从主机通过南行车道作为串行数据包发送的内存请求。 AMB从串行数据包中提取存储器访问地址。 修复控制器将存储器访问地址与修复地址进行比较，并将从缺陷存储器芯片的访问转移到用于修复地址的备用存储器。 修复地址可以在测试存储器模块期间定位并编程到AMB上的修复地址缓冲区中。 修复地址可以首先编程到存储器模块上的串行存在检测电可擦除可编程只读存储器（SPD-EEPROM）中，然后在上电期间复制到AMB上的修复地址缓冲区。

公开(公告)号：US20080222367A1

公开(公告)日：2008-09-11

申请号：US12115200

申请日：2008-05-05

申请人： Ramon S. Co

发明人： Ramon S. Co

IPC分类号： G06F12/00

CPC分类号： G06F13/1684 ,  G06F13/1673 ,  G11C5/04 ,  Y02D10/14

摘要： A branching memory-bus module has one uplink port and two or more downlink ports. Frames sent downstream by a host processor are received on the uplink port and repeated to the multiple downlink ports to two or more branches of memory modules. Frames sent upstream to the processor by a memory module on a downlink port are repeated to the uplink port. A branching Advanced Memory Buffer (AMB) on the branching memory-bus module has re-timing and re-synchronizing buffers that repeat frames to the multiple downlink ports. Elastic buffers can merge and synchronize frames from different downlink branches. Separate northbound and southbound lanes may be replaced by bidirectional lanes to reduce pin counts. Latency from the host processor to the farthest memory module is reduced by branching compared with a serial daisy-chain of fully-buffered memory modules. Point-to-point bus segments have only two endpoints despite branching by the branching AMB.

摘要翻译： 分支存储器总线模块具有一个上行链路端口和两个或更多个下行链路端口。 在主机处理器发送的下游的帧在上行链路端口上被接收并且被重复到多个下行链路端口到存储器模块的两个或更多个分支。 通过下行链路端口上的存储器模块向处理器上行发送的帧被重复到上行链路端口。 分支存储器总线模块上的分支高级存储器缓冲器（AMB）具有对多个下行链路端口重复帧的重新定时和重新同步缓冲器。 弹性缓冲区可以合并和同步来自不同下行链路分支的帧。 分开的北行和南行车道可以由双向车道代替，以减少销数。 与串行菊花链完全缓冲的内存模块相比，从主处理器到最远的内存模块的延迟减少了。 点对点总线段只有两个端点，尽管分支AMB分支。

公开(公告)号：US20080165600A1

公开(公告)日：2008-07-10

申请号：US12053261

申请日：2008-03-21

申请人： Ramon S. Co ,  David Sun

发明人： Ramon S. Co ,  David Sun

IPC分类号： G11C29/00 ,  G11C8/00

CPC分类号： G11C5/04 ,  G11C29/808 ,  G11C29/88

摘要： A repairing fully-buffered memory module can have memory chips with some defects such as single-bit errors. A repair controller is added to the Advanced Memory Buffer (AMB) on the memory module. The AMB fully buffers memory requests that are sent as serial packets over southbound lanes from a host. Memory-access addresses are extracted from the serial packets by the AMB. The repair controller compares the memory-access addresses to repair addresses and diverts access from defective memory chips to a spare memory for the repair addresses. The repair addresses can be located during testing of the memory module and programmed into a repair address buffer on the AMB. The repair addresses could be first programmed into a serial-presence-detect electrically-erasable programmable read-only memory (SPD-EEPROM) on the memory module, and then copied to the repair address buffer on the AMB during power-up.

摘要翻译： 修复全缓冲存储器模块可以具有存在诸如单位错误等缺陷的存储器芯片。 修复控制器被添加到内存模块的高级内存缓冲区（AMB）中。 AMB完全缓冲从主机通过南行车道作为串行数据包发送的内存请求。 AMB从串行数据包中提取存储器访问地址。 修复控制器将存储器访问地址与修复地址进行比较，并将从缺陷存储器芯片的访问转移到用于修复地址的备用存储器。 修复地址可以在测试存储器模块期间定位并编程到AMB上的修复地址缓冲区中。 修复地址可以首先编程到存储器模块上的串行存在检测电可擦除可编程只读存储器（SPD-EEPROM）中，然后在上电期间复制到AMB上的修复地址缓冲区。

公开(公告)号：US5325400A

公开(公告)日：1994-06-28

申请号：US893468

申请日：1992-06-04

申请人： Ramon S. Co ,  Ron Kao

发明人： Ramon S. Co ,  Ron Kao

IPC分类号： H04L25/02 ,  H04L25/03 ,  H04L25/49

CPC分类号： H04L25/0286 ,  H04L25/03343 ,  H04L25/03834 ,  H04L25/0266

摘要： A method and apparatus for predistorting digital signals so as to minimize radiation of harmonic signal energy during data transmission. The programmable waveshaping apparatus of the present invention is operative to predistort a binary encoded waveform to be transmitted over a transmission line. A pulse discriminator circuit is disposed to indicate the receipt of each pulse within an input sequence of short and long pulses included within the encoded waveform. Upon receipt of each short and long pulse an input logic network generates first and second sets of control signals, respectively. The logic network synthesizes the control signals based on information relating to sampled approximations of filtered versions of the short and long pulses. The inventive waveshaping apparatus further includes a programmable electrical source array for generating a sequence of line driving signals in accordance with each set of control signals. A transformer driver then pulses the transmission line in response to the driving signals in order to transmit information included within the encoded input sequence.

摘要翻译： 一种用于预失真数字信号以便在数据传输期间最小化谐波信号能量的辐射的方法和装置。 本发明的可编程波形整形装置可用于对要在传输线上传输的二进制编码波形进行预失真。 设置脉冲鉴别器电路以指示包含在编码波形内的短脉冲和长脉冲的输入序列内的每个脉冲的接收。 在输入逻辑网络接收到每个短脉冲和长脉冲时，分别产生第一和第二组控制信号。 逻辑网络基于与短脉冲和长脉冲的滤波版本的采样近似相关的信息来合成控制信号。 本发明的波形成形装置还包括可编程电源阵列，用于根据每组控制信号产生一系列线路驱动信号。 然后，变压器驱动器响应于驱动信号脉冲传输线，以便发送包括在编码输入序列内的信息。

公开(公告)号：US08022721B2

公开(公告)日：2011-09-20

申请号：US13089108

申请日：2011-04-18

申请人： Ramon S. Co ,  Kevin J. Sun

发明人： Ramon S. Co ,  Kevin J. Sun

IPC分类号： G01R31/20

CPC分类号： G11C29/56 ,  B65G47/71 ,  G11C5/04 ,  G11C29/56016

摘要： A conveyor-stack test system has motherboards that test memory modules. The motherboards are not stationary but are placed inside movable trays that move along conveyors. A loader-unloader removes tested memory modules from test sockets on the motherboards and inserts untested memory modules into the motherboards using a robotic arm. A conveyor carries the motherboards from the loader-unloader to an elevator. The elevator raises or lowers the motherboards to different levels in a conveyor stack with multiple levels of conveyors each with many test stations. The motherboards move along conveyors in the conveyor stack until reaching test stations. A retractable connector from the test station extends to make contact with a motherboard connector to power up the motherboard, which then tests the memory modules. Test results are communicated from the test station to a host controller, which instructs the loader-unloader to sort the tested memory modules once the motherboard returns.

公开(公告)号：US07904655B2

公开(公告)日：2011-03-08

申请号：US12115200

申请日：2008-05-05

申请人： Ramon S. Co

发明人： Ramon S. Co

IPC分类号： G06F13/28

CPC分类号： G06F13/1684 ,  G06F13/1673 ,  G11C5/04 ,  Y02D10/14

摘要： A branching memory-bus module has one uplink port and two or more downlink ports. Frames sent downstream by a host processor are received on the uplink port and repeated to the multiple downlink ports to two or more branches of memory modules. Frames sent upstream to the processor by a memory module on a downlink port are repeated to the uplink port. A branching Advanced Memory Buffer (AMB) on the branching memory-bus module has re-timing and re-synchronizing buffers that repeat frames to the multiple downlink ports. Elastic buffers can merge and synchronize frames from different downlink branches. Separate northbound and southbound lanes may be replaced by bidirectional lanes to reduce pin counts. Latency from the host processor to the farthest memory module is reduced by branching compared with a serial daisy-chain of fully-buffered memory modules. Point-to-point bus segments have only two endpoints despite branching by the branching AMB.

摘要翻译： 分支存储器总线模块具有一个上行链路端口和两个或更多个下行链路端口。 在主机处理器发送的下游的帧在上行链路端口上被接收并且被重复到多个下行链路端口到存储器模块的两个或更多个分支。 通过下行链路端口上的存储器模块向处理器上行发送的帧被重复到上行链路端口。 分支存储器总线模块上的分支高级存储器缓冲器（AMB）具有对多个下行链路端口重复帧的重新定时和重新同步缓冲器。 弹性缓冲区可以合并和同步来自不同下行链路分支的帧。 分开的北行和南行车道可以由双向车道代替，以减少销数。 与串行菊花链完全缓冲的内存模块相比，从主处理器到最远的内存模块的延迟减少了。 点对点总线段只有两个端点，尽管分支AMB分支。

公开(公告)号：US20110050268A1

公开(公告)日：2011-03-03

申请号：US12941196

申请日：2010-11-08

申请人： Ramon S. Co ,  Kevin J. Sun

发明人： Ramon S. Co ,  Kevin J. Sun

IPC分类号： G01R31/20

CPC分类号： G11C29/56 ,  G11C29/56016

摘要： A parking-structure test system has motherboards that test memory modules. The motherboards are not stationary but are placed inside movable trays that move along conveyors. An unloader removes tested memory modules from test sockets on the motherboards, and a loader inserts untested memory modules into the motherboards using a robotic arm. A conveyor carries the motherboards from the loader to a parking and testing structure. An elevator raises or lowers the motherboards to different parking levels in the parking and testing structure. The motherboards move from the elevator to test stations on the parking level. A retractable connector from the test station makes contact with a motherboard connector to power up the motherboard, which then tests the memory modules. Test results are communicated from the test station to a host controller, which instructs the loader-unloader to sort the tested memory modules once the motherboard returns via the elevator and conveyors.