公开(公告)号：US20230297818A1

公开(公告)日：2023-09-21

申请号：US18184550

申请日：2023-03-15

Applicant: Rebellions Inc.

Inventor： Jinwook Oh

IPC: G06N3/063

CPC classification number: G06N3/063

Abstract: A neural processing device processing circuitry comprising and method for controlling the same are provided. The neural processing device comprises at least one processing engine group each of which includes at least one processing engines, a first memory shared by the at least one processing engine group, and an interconnection configured to exchange data between the at least one processing engine group and the first memory. The processing circuitry is configured to monitor the at least one processing engine to check performance related to the at least one processing engine, and provide hardware resources to at least one of the first memory, the interconnection or the at least one processing engine, according to the performance.

公开(公告)号：US20230297817A1

公开(公告)日：2023-09-21

申请号：US18184543

申请日：2023-03-15

Applicant: Rebellions Inc.

Inventor： Jinwook Oh

IPC: G06N3/063

CPC classification number: G06N3/063

Abstract: A neural processing device comprising processing circuitry are provided. A neural processing device comprises a plurality of processing engine groups; a first memory shared by the plurality of engine groups; a first interconnection configured to transmit data between the first memory and the plurality of processing engine groups. The neural processing device is configured to provide hardware resource to the plurality of processing engine groups. The at least one of the plurality of processing engine groups comprises a plurality of processing engines, each of the plurality of processing engines comprising an array of a plurality of processing elements interconnected by a mesh style network, the processing elements being reconfigurable; a second memory shared by the plurality of processing engines; and a second interconnection configured to transmit data between the second memory and the plurality of processing engines.

公开(公告)号：US11657261B1

公开(公告)日：2023-05-23

申请号：US17661414

申请日：2022-04-29

Applicant: Rebellions Inc.

Inventor： Jinwook Oh ,  Jinseok Kim ,  Kyeongryeol Bong ,  Wongyu Shin ,  Chang-Hyo Yu

IPC: G06N3/063 ,  G06F9/38 ,  G06F9/52 ,  G06F5/06

CPC classification number: G06N3/063 ,  G06F5/065 ,  G06F9/3877 ,  G06F9/52

Abstract: A neural processing device is provided. The neural processing device comprises a plurality of neural processors, a shared memory shared by the plurality of neural processors, a plurality of semaphore memories, and global interconnection. The plurality of neural processors generates a plurality of L3 sync targets, respectively. Each semaphore memory is associated with a respective one of the plurality of neural processors, and the plurality of semaphore memories receive and store the plurality of L3 sync targets, respectively. Synchronization of the plurality of neural processors is performed according to the plurality of L3 sync targets. The global interconnection connects the plurality of neural processors with the shared memory, and comprises an L3 sync channel through which an L3 synchronization signal corresponding to at least one L3 sync target is transmitted.

公开(公告)号：US20220300254A1

公开(公告)日：2022-09-22

申请号：US17655737

申请日：2022-03-21

Applicant: Rebellions Inc.

Inventor： Jinwook Oh

IPC: G06F7/544 ,  G06N3/063

Abstract: A processing element, a neural processing device including the same, and a method for calculating thereof are provided. The processing element includes a weight register configured to receive and store weights, an input activation register configured to store input activations, a flexible multiplier configured to receive the weight and the input activation, to perform a multiplication calculation in a first precision or a second precision different from the first precision according to a mode signal, occurrence of an overflow, and occurrence of an underflow, and to generates result data; and a saturating adder configured to receive the result data and generate subtotals.

公开(公告)号：US12174741B2

公开(公告)日：2024-12-24

申请号：US18448102

申请日：2023-08-10

Applicant: Rebellions Inc.

Inventor： Jinseok Kim ,  Jinwook Oh ,  Donghan Kim

IPC: G06F12/084

Abstract: A neural processing device is provided. The neural processing device comprises: a processing unit configured to perform calculations, an L0 memory configured to receive data from the processing unit and provide data to the processing unit, and an LSU (Load/Store Unit) configured to perform load and store operations of the data, wherein the LSU comprises: a neural core load unit configured to issue a load instruction of the data, a neural core store unit configured to issue a store instruction for transmitting and storing the data, and a sync ID logic configured to provide a sync ID to the neural core load unit and the neural core store unit to thereby cause a synchronization signal to be generated for each sync ID.

公开(公告)号：US12073312B2

公开(公告)日：2024-08-27

申请号：US18184550

申请日：2023-03-15

Applicant: Rebellions Inc.

Inventor： Jinwook Oh

IPC: G06F9/46 ,  G06F9/50 ,  G06F13/14 ,  G06N3/063

CPC classification number: G06N3/063 ,  G06F9/5011 ,  G06F13/14 ,  G06F2209/501 ,  G06F2209/508

Abstract: A neural processing device processing circuitry comprising and method for controlling the same are provided. The neural processing device comprises at least one processing engine group each of which includes at least one processing engines, a first memory shared by the at least one processing engine group, and an interconnection configured to exchange data between the at least one processing engine group and the first memory. The processing circuitry is configured to monitor the at least one processing engine to check performance related to the at least one processing engine, and provide hardware resources to at least one of the first memory, the interconnection or the at least one processing engine, according to the performance.

公开(公告)号：US12032996B2

公开(公告)日：2024-07-09

申请号：US18491695

申请日：2023-10-20

Applicant: Rebellions Inc.

Inventor： Wongyu Shin ,  Miock Chi ,  Hongyun Kim ,  Jinwook Oh ,  Juyeong Yoon

IPC: G06F9/48 ,  G06F9/38

CPC classification number: G06F9/4881 ,  G06F9/3838

Abstract: A neural processing device and a method for managing tasks thereof are provided. The neural processing device includes a neural core configured to perform a task and generate a completion signal for completion of the task, a core global configured to transfer task information for the task to the neural core and receive the completion signal of the task from the neural core, and a task manager configured to generate and transmit the task information to the core global, receive the completion signal from the core global, generate a completion report, and transmit the completion report.

公开(公告)号：US20240220246A1

公开(公告)日：2024-07-04

申请号：US18602924

申请日：2024-03-12

Applicant: Rebellions Inc.

Inventor： Karim Charfi ,  Jinwook Oh

IPC: G06F9/30

CPC classification number: G06F9/30025 ,  G06F9/3001 ,  G06F9/30098

Abstract: A neural processing device, a processing element included therein and a method for operating various formats of the neural processing device are provided. The neural processing device includes at least one neural processor, a shared memory shared by the at least one neural processor, and a global interconnection configured to transmit data between the at least one neural processor and the shared memory, wherein each of the at least one neural processor comprises at least one processing element, each of the at least one processing element receives an input in a first format and thereby performs an operation, and receives an input in a second format that is different from the first format and thereby performs an operation if a format conversion signal is received, and the first format and the second format have a same number of bits.

公开(公告)号：US20230315639A1

公开(公告)日：2023-10-05

申请号：US18057183

申请日：2022-11-18

Applicant: Rebellions Inc.

Inventor： Jinseok Kim ,  Jinwook Oh ,  Donghan Kim

IPC: G06F12/084

CPC classification number: G06F12/084 ,  G06F2212/622

Abstract: A neural processing device is provided. The neural processing device comprises: a processing unit configured to perform calculations, an L0 memory configured to receive data from the processing unit and provide data to the processing unit, and an LSU (Load/Store Unit) configured to perform load and store operations of the data, wherein the LSU comprises: a neural core load unit configured to issue a load instruction of the data, a neural core store unit configured to issue a store instruction for transmitting and storing the data, and a sync ID logic configured to provide a sync ID to the neural core load unit and the neural core store unit to thereby cause a synchronization signal to be generated for each sync ID.

公开(公告)号：US11775437B1

公开(公告)日：2023-10-03

申请号：US18057183

申请日：2022-11-18

Applicant: Rebellions Inc.

Inventor： Jinseok Kim ,  Jinwook Oh ,  Donghan Kim

IPC: G06F12/084

CPC classification number: G06F12/084 ,  G06F2212/622

Abstract: A neural processing device is provided. The neural processing device comprises: a processing unit configured to perform calculations, an L0 memory configured to receive data from the processing unit and provide data to the processing unit, and an LSU (Load/Store Unit) configured to perform load and store operations of the data, wherein the LSU comprises: a neural core load unit configured to issue a load instruction of the data, a neural core store unit configured to issue a store instruction for transmitting and storing the data, and a sync ID logic configured to provide a sync ID to the neural core load unit and the neural core store unit to thereby cause a synchronization signal to be generated for each sync ID.