公开(公告)号：US20240378157A1

公开(公告)日：2024-11-14

申请号：US18733709

申请日：2024-06-04

Applicant: Rebellions Inc.

Inventor： Chang-Hyo Yu

IPC: G06F12/1027 ,  G06N3/04 ,  G06N3/08

Abstract: A neural processing device and a method of updating translation lookaside buffer thereof are provided. The neural processing device includes at least one processor module each of which includes at least one micro translation lookaside buffer (TLB), a hierarchical memory that is accessed by the at least one micro TLB, and a command processor configured to update the at least one micro TLB in a push mode by generating a first update signal which indicates update of the at least one micro TLB and transmitting the first update signal to the at least one micro TLB.

公开(公告)号：US20240330041A1

公开(公告)日：2024-10-03

申请号：US18621936

申请日：2024-03-29

Applicant: REBELLIONS INC.

Inventor： Hongyun Kim ,  Chang-Hyo Yu ,  Yoonho Boo

IPC: G06F9/48 ,  G06F9/54 ,  G06F12/0831

CPC classification number: G06F9/4856 ,  G06F9/544 ,  G06F12/0835

Abstract: A command processor determines whether a command descriptor describing a current command is in a first format or in a second format, wherein the first format includes a source memory address pointing to a memory area in a shared memory having a binary code to be accessed according to direct memory access (DMA) scheme, and the second format includes one or more object indices, a respective one of the one or more object indices indicating an object in an object database. If the command descriptor describing the current command is in the second format, the command processor converts a format of the command descriptor to the first format, generates one or more task descriptors describing neural network model tasks based on the command descriptor in the first format, and distributes the one or more task descriptors to the one or more neural processors.

公开(公告)号：US20240256714A1

公开(公告)日：2024-08-01

申请号：US18521890

申请日：2023-11-28

Applicant: REBELLIONS INC.

Inventor： Myunghoon Choi ,  Chang-Hyo Yu

IPC: G06F21/64 ,  G06F21/60 ,  G06F21/74 ,  G06F21/78

CPC classification number: G06F21/64 ,  G06F21/602 ,  G06F21/74 ,  G06F21/78

Abstract: A method for runtime integrity check, performed by a security core including one or more processors includes storing a first output value, which is generated by using a one-way encryption algorithm based on first data and a first encryption key managed by an encryption key manager accessible by the security core, in a main memory that is a volatile memory in association with the first data, generating a second output value for the first data based on the first data and the first encryption key by using the one-way encryption algorithm, and checking for possible tampering of the first data stored in the main memory by comparing the first output value with the generated second output value.

公开(公告)号：US20230244920A1

公开(公告)日：2023-08-03

申请号：US18298935

申请日：2023-04-11

Applicant: Rebellions Inc.

Inventor： Jinwook Oh ,  Jinseok Kim ,  Kyeongryeol Bong ,  Wongyu Shin ,  Chang-Hyo Yu

IPC: G06N3/063 ,  G06F5/06 ,  G06F9/38 ,  G06F9/52

CPC classification number: G06N3/063 ,  G06F5/065 ,  G06F9/3877 ,  G06F9/52

Abstract: A neural processing device is provided. The neural processing device comprises a plurality of neural processors, a shared memory shared by the plurality of neural processors, a plurality of semaphore memories, and global interconnection. The plurality of neural processors generates a plurality of L3 sync targets, respectively. Each semaphore memory is associated with a respective one of the plurality of neural processors, and the plurality of semaphore memories receive and store the plurality of L3 sync targets, respectively. Synchronization of the plurality of neural processors is performed according to the plurality of L3 sync targets. The global interconnection connects the plurality of neural processors with the shared memory, and comprises an L3 sync channel through which an L3 synchronization signal corresponding to at least one L3 sync target is transmitted.

公开(公告)号：US20250068521A1

公开(公告)日：2025-02-27

申请号：US18809049

申请日：2024-08-19

Applicant: REBELLIONS INC.

Inventor： Myunghoon Choi ,  Chang-Hyo Yu

IPC: G06F21/57 ,  G06F21/55

Abstract: An electronic device comprises a main chiplet including a first memory and at least one sub-chiplet including a second memory, wherein the main chiplet is configured to initialize a first interface for inter-chiplet connection based on first boot firmware stored in the first memory in response to receiving booting signal, acquire third boot firmware stored in an external memory, initialize a second interface for communication between an external device and the main chiplet based on the third boot firmware, set a configuration for interconnection between the main chiplet and the at least one sub-chiplet, initialize a third memory included in the main chiplet, and load at least one of an application firmware or an operating system to the third memory, and the at least one sub-chiplet is configured to initialize the first interface based on second boot firmware stored in the second memory in response to receiving the booting signal.

公开(公告)号：US12038850B1

公开(公告)日：2024-07-16

申请号：US18500781

申请日：2023-11-02

Applicant: Rebellions Inc.

Inventor： Chang-Hyo Yu

IPC: G06F12/1027 ,  G06N3/04 ,  G06N3/08

CPC classification number: G06F12/1027 ,  G06N3/04 ,  G06N3/08

Abstract: A neural processing device and a method of updating translation lookaside buffer thereof are provided. The neural processing device includes at least one processor module each of which includes at least one micro translation lookaside buffer (TLB), a hierarchical memory that is accessed by the at least one micro TLB, and a command processor configured to update the at least one micro TLB in a push mode by generating a first update signal which indicates update of the at least one micro TLB and transmitting the first update signal to the at least one micro TLB.

公开(公告)号：US12229587B2

公开(公告)日：2025-02-18

申请号：US18621936

申请日：2024-03-29

Applicant: REBELLIONS INC.

Inventor： Hongyun Kim ,  Chang-Hyo Yu ,  Yoonho Boo

IPC: G06F9/48 ,  G06F9/54 ,  G06F12/0831

Abstract: A command processor determines whether a command descriptor describing a current command is in a first format or in a second format, wherein the first format includes a source memory address pointing to a memory area in a shared memory having a binary code to be accessed according to direct memory access (DMA) scheme, and the second format includes one or more object indices, a respective one of the one or more object indices indicating an object in an object database. If the command descriptor describing the current command is in the second format, the command processor converts a format of the command descriptor to the first format, generates one or more task descriptors describing neural network model tasks based on the command descriptor in the first format, and distributes the one or more task descriptors to the one or more neural processors.

公开(公告)号：US20240296245A1

公开(公告)日：2024-09-05

申请号：US18658736

申请日：2024-05-08

Applicant: REBELLIONS INC.

Inventor： Myunghoon Choi ,  Chang-Hyo Yu

IPC: G06F21/62

CPC classification number: G06F21/6227

Abstract: A method for confidential computing is provided, which is performed by a security core including one or more processor, and includes storing first encrypted data associated with a first tenant in a first memory, in which the first encrypted data is obtained by performing encryption of the first plaintext data using a first encryption key associated with the first tenant, in response to receiving a request to access the first plaintext data, decrypting the first encrypted data using the first encryption key so as to generate the first plaintext data, and providing the first plaintext data to a main core that processes data stored in the first memory.

公开(公告)号：US11874953B1

公开(公告)日：2024-01-16

申请号：US18338258

申请日：2023-06-20

Applicant: REBELLIONS INC.

Inventor： Myunghoon Choi ,  Chang-Hyo Yu

IPC: G06F21/64 ,  G06F21/60 ,  G06F21/74 ,  G06F21/78

CPC classification number: G06F21/64 ,  G06F21/602 ,  G06F21/74 ,  G06F21/78

Abstract: A method for runtime integrity check, performed by a security core including one or more processors includes storing a first output value, which is generated by using a one-way encryption algorithm based on first data and a first encryption key managed by an encryption key manager accessible by the security core, in a main memory that is a volatile memory in association with the first data, generating a second output value for the first data based on the first data and the first encryption key by using the one-way encryption algorithm, and checking for possible tampering of the first data stored in the main memory by comparing the first output value with the generated second output value.

公开(公告)号：US20240311186A1

公开(公告)日：2024-09-19

申请号：US18671802

申请日：2024-05-22

Applicant: Rebellions Inc.

Inventor： Wongyu Shin ,  Miock Chi ,  Hongyun Kim ,  Jinseok Kim ,  Chang-Hyo Yu

IPC: G06F9/48

CPC classification number: G06F9/4881

Abstract: A task manager, a neural processing device, and a method for checking task dependencies thereof are provided. The task manager includes a task buffer configured to receive first and second tasks of different first and second types, a first queue configured to receive a first task descriptor for the first task from the task buffer, a second queue configured to receive a second task descriptor for the second task from the task buffer, a dependency checker configured to check dependencies of the first and second task descriptors, a third queue configured to receive the first task descriptor from the dependency checker, and a fourth queue configured to receive the second task descriptor from the dependency checker.