公开(公告)号：US20220247311A1

公开(公告)日：2022-08-04

申请号：US17571741

申请日：2022-01-10

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Sebastien Ortet

IPC: H02M3/158 ,  H02M3/157

Abstract: In an embodiment, a device includes a switching power supply configured to have a first operating mode synchronized by a first clock signal generated by a clock generator a second asynchronous operating mode. The clock generator is configured such that the first clock signal becomes equal, upon transition from the second operating mode to the first operating mode, to the signal having the closest rising edge of a second clock signal and a third clock signal complementary to the second clock signal.

公开(公告)号：US11139676B2

公开(公告)日：2021-10-05

申请号：US16267968

申请日：2019-02-05

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Laurent Truphemus ,  Sebastien Ortet

IPC: H02J9/00 ,  G06F1/26 ,  G06F1/30 ,  G11C5/14 ,  G11C11/4074 ,  G11C16/30 ,  G11C11/40

Abstract: An integrated circuit includes: a primary supply stage including a primary supply node, the primary supply stage being configured to deliver a primary supply voltage to the primary supply node; a secondary supply stage including a secondary supply node, the secondary supply stage being configured to deliver a secondary supply voltage to the secondary supply node; a supply-switching circuit; a pre-charging circuit controllably coupled to the secondary supply node via the supply-switching circuit; and a volatile memory circuit controllably coupled to the primary supply node and the secondary supply node via the supply-switching circuit, wherein the switching circuit is configured to connect a supply of the volatile memory circuit either to the primary supply node in a primary supply mode, or to the secondary supply node in a secondary supply mode.