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    Switched mode power supply (SMPS)
    2.
    发明授权
    Switched mode power supply (SMPS) 有权

    公开(公告)号：US12143015B2

    公开(公告)日：2024-11-12

    申请号：US17731000

    申请日：2022-04-27

    Applicant: STMicroelectronics (Rousset) SAS

    Inventor： Sebastien Ortet

    IPC: H02M3/158

    Abstract: In an embodiment a switching power supply includes a voltage ramp generator comprising at least one output capacitor, wherein the generator is configured such that the output capacitor has a first value during a first operating cycle of a first operating mode and a second value during subsequent operating cycles of the first operating mode.

    Synchronization of an electronic device
    3.
    发明授权
    Synchronization of an electronic device 有权

    公开(公告)号：US12107504B2

    公开(公告)日：2024-10-01

    申请号：US17571759

    申请日：2022-01-10

    Applicant: STMicroelectronics (Rousset) SAS

    Inventor： Sebastien Ortet ,  Vincent Binet

    IPC: H02M3/158 ,  H02M1/00

    CPC classification number: H02M3/1588 ,  H02M1/0009

    Abstract: In an embodiment, a switching power supply includes: an output stage; a clock generator configured to generate a first clock signal; and a control circuit configured to control the output stage based on the first clock signal, wherein the switching power supply is configured to have a first operating mode synchronized by the first clock signal, and a second operating mode that is asynchronous, wherein the clock generator is configured to maintain the first clock signal at a constant value during the second operating mode.

    Switched-mode power supply having multiple operating phases
    5.
    发明授权
    Switched-mode power supply having multiple operating phases 有权

    公开(公告)号：US10862396B2

    公开(公告)日：2020-12-08

    申请号：US16599450

    申请日：2019-10-11

    Applicant: STMicroelectronics (Rousset) SAS

    Inventor： Sebastien Ortet ,  Didier Davino ,  Cedric Thomas

    IPC: H02M3/158 ,  H02M1/36

    Abstract: An electronic device includes a switched-mode power supply having a first operating phase during which the output node of the switched-mode power supply is coupled by an on switch to a source of a first reference voltage. The first operating phase is followed by a second operation phase during which the output node of the switched-mode power supply is in a high impedance state. While in the second operating phase, a capacitor connected to the output node of the switched-mode power supply at least partially discharges into a load.

    Voltage comparator and method
    6.
    发明授权
    Voltage comparator and method 有权

    公开(公告)号：US11736018B2

    公开(公告)日：2023-08-22

    申请号：US17370609

    申请日：2021-07-08

    Applicant: STMicroelectronics (Rousset) SAS

    Inventor： Sebastien Ortet ,  Didier Davino

    IPC: H02M3/158 ,  H02M1/00

    CPC classification number: H02M3/1588 ,  H02M1/0009 ,  H02M1/0025

    Abstract: An embodiment electronic device includes a first circuit including first and second transistors series-coupled between a node of application of a power supply voltage and a node of application of a reference voltage, the first and second transistors being coupled to each other by a first node, and a second circuit, configured to compare a first voltage on the first node with first and second voltage thresholds.

    SYNCHRONIZATION OF AN ELECTRONIC DEVICE
    8.
    发明申请
    SYNCHRONIZATION OF AN ELECTRONIC DEVICE 有权

    公开(公告)号：US20220247318A1

    公开(公告)日：2022-08-04

    申请号：US17571759

    申请日：2022-01-10

    Applicant: STMicroelectronics (Rousset) SAS

    Inventor： Sebastien Ortet ,  Vincent Binet

    IPC: H02M3/158 ,  H02M1/00

    Abstract: In an embodiment, a switching power supply includes: an output stage; a clock generator configured to generate a first clock signal; and a control circuit configured to control the output stage based on the first clock signal, wherein the switching power supply is configured to have a first operating mode synchronized by the first clock signal, and a second operating mode that is asynchronous, wherein the clock generator is configured to maintain the first clock signal at a constant value during the second operating mode.

    METHOD FOR PRECHARGING AN INTEGRATED-CIRCUIT SUPPLY, AND CORRESPONDING INTEGRATED CIRCUIT
    9.
    发明申请
    METHOD FOR PRECHARGING AN INTEGRATED-CIRCUIT SUPPLY, AND CORRESPONDING INTEGRATED CIRCUIT 有权

    公开(公告)号：US20210391744A1

    公开(公告)日：2021-12-16

    申请号：US17459465

    申请日：2021-08-27

    Applicant: STMicroelectronics (Rousset) SAS

    Inventor： Laurent Truphemus ,  Sebastien Ortet

    IPC: H02J9/00 ,  G06F1/26 ,  G06F1/30 ,  G11C5/14 ,  G11C11/4074 ,  G11C16/30

    Abstract: An integrated circuit includes: a primary supply stage including a primary supply node, the primary supply stage being configured to deliver a primary supply voltage to the primary supply node; a secondary supply stage including a secondary supply node, the secondary supply stage being configured to deliver a secondary supply voltage to the secondary supply node; a supply-switching circuit; a pre-charging circuit controllably coupled to the secondary supply node via the supply-switching circuit; and a volatile memory circuit controllably coupled to the primary supply node and the secondary supply node via the supply-switching circuit, wherein the switching circuit is configured to connect a supply of the volatile memory circuit either to the primary supply node in a primary supply mode, or to the secondary supply node in a secondary supply mode.

    Voltage converter and method
    10.
    发明授权
    Voltage converter and method 有权

    公开(公告)号：US11967900B2

    公开(公告)日：2024-04-23

    申请号：US17366353

    申请日：2021-07-02

    Applicant: STMicroelectronics (Rousset) SAS

    Inventor： Sebastien Ortet ,  Olivier Lauzier

    IPC: H02M3/158 ,  H02M1/00 ,  H02M1/36

    CPC classification number: H02M3/158 ,  H02M1/0032 ,  H02M1/0083 ,  H02M1/36

    Abstract: An embodiment voltage converter includes a first transistor connected between a first node of the converter and a second node configured to receive a power supply voltage, a second transistor connected between the first node and a third node configured to receive a reference potential, a first circuit configured to control the first and second transistors, and a comparator including first and second inputs. The first input is configured to receive, during a first phase, a first voltage ramp and, during a second phase, a set point voltage. The second input is configured to receive, during the first phase, the set point voltage and, during the second phase, a second voltage ramp.

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