公开(公告)号：US20150049103A1

公开(公告)日：2015-02-19

申请号：US14526692

申请日：2014-10-29

Applicant: SAMSUNG DISPLAY CO., LTD.

Inventor： Masayuki KUMETA ,  Ryo ISHII ,  Kazuhiro MATSUMOTO ,  Shinji YAMASHITA ,  Ansu LEE

IPC: G09G5/39

CPC classification number: G09G5/39 ,  G09G3/20 ,  G09G5/005 ,  G09G2310/0224 ,  G09G2310/0235 ,  G09G2310/08 ,  G09G2360/12 ,  G09G2360/18

Abstract: A control circuit for a frame memory includes a divider, a frame memory, a read control circuit, and a write control circuit. The divider divides image data into subfield data according to a plurality of subfields, where the image data is provided in synchronization with a first synchronization signal and in a unit of a frame. The frame memory has a plurality of blocks to store the subfield data. The read control circuit sequentially reads the subfield data from the blocks in synchronization with a second synchronization signal. The write control circuit writes new data to a first block before data written in a second block is read, and after data written in the first block is read by the read control circuit. The second synchronization signal may have a same cycle as the first synchronization signal and may be delayed by a preset delay time.

Abstract translation: 用于帧存储器的控制电路包括分频器，帧存储器，读控制电路和写控制电路。 分配器根据多个子场将图像数据分割成子场数据，其中图像数据与第一同步信号同步地以帧为单位提供。 帧存储器具有存储子场数据的多个块。 读取控制电路与第二同步信号同步地从块中顺序地读取子场数据。 写入控制电路在读取写入第二块中的数据之前并且在读取控制电路读取写入第一块的数据之后，将新数据写入第一块。 第二同步信号可以具有与第一同步信号相同的周期，并且可以延迟预设的延迟时间。

公开(公告)号：US20150002558A1

公开(公告)日：2015-01-01

申请号：US14321002

申请日：2014-07-01

Applicant: SAMSUNG DISPLAY CO., LTD.

Inventor： Masayuki KUMETA ,  Takeshi OKUNO ,  Eiji KANDA ,  Ryo ISHII ,  Naoaki KOMIYA

IPC: G09G3/36 ,  G09G3/32

CPC classification number: G09G3/3258 ,  G09G3/2007 ,  G09G3/3233 ,  G09G3/3291 ,  G09G2300/043 ,  G09G2300/0809 ,  G09G2300/0819 ,  G09G2300/0842 ,  G09G2310/0262 ,  G09G2320/045

Abstract: A pixel includes five transistors and a capacitor. A first transistor controls current to be supplied to a light-emitting element. A second transistor is connected between a gate electrode of the first transistor and a first power supply. A third transistor is connected between the gate electrode of the first transistor and a second terminal of the first transistor. The capacitor is coupled between the third transistor and the second terminal of the first transistor. The fourth transistor is connected between the second terminal of the first transistor and a second power supply. The fifth transistor is connected between the second terminal of the third transistor and a signal line. The capacitor may be the only capacitor in the pixel, and the signal line may receive an initialization voltage and a gray scale data voltage.

Abstract translation: 像素包括五个晶体管和一个电容器。 第一晶体管控制提供给发光元件的电流。 第二晶体管连接在第一晶体管的栅电极和第一电源之间。 第三晶体管连接在第一晶体管的栅电极和第一晶体管的第二端之间。 电容器耦合在第三晶体管和第一晶体管的第二端子之间。 第四晶体管连接在第一晶体管的第二端和第二电源之间。 第五晶体管连接在第三晶体管的第二端和信号线之间。 电容器可以是像素中的唯一电容器，信号线可以接收初始化电压和灰度数据电压。

公开(公告)号：US20140327664A1

公开(公告)日：2014-11-06

申请号：US14265830

申请日：2014-04-30

Applicant: SAMSUNG DISPLAY CO., LTD.

Inventor： Eiji KANDA ,  Masayuki KUMETA

IPC: G09G3/32

CPC classification number: G09G3/3233 ,  G09G2300/0852 ,  G09G2300/0861

Abstract: A pixel circuit includes a first transistor coupled to a light emitting element, a first capacitor coupled to the first transistor, a second transistor coupled to the first capacitor, a third transistor coupled between the second transistor and a data line; and a second capacitor having a first electrode coupled between the second and third transistors. The first transistor controls an amount of current supplied to the light emitting element based on a first data voltage while a second data voltage is stored in the second capacitor. The first data voltage is stored in the first capacitor.

Abstract translation: 像素电路包括耦合到发光元件的第一晶体管，耦合到第一晶体管的第一电容器，耦合到第一电容器的第二晶体管，耦合在第二晶体管和数据线之间的第三晶体管; 以及第二电容器，其具有耦合在第二和第三晶体管之间的第一电极。 第一晶体管基于第一数据电压控制提供给发光元件的电流量，而第二数据电压存储在第二电容器中。 第一数据电压存储在第一电容器中。