公开(公告)号：US20240389394A1

公开(公告)日：2024-11-21

申请号：US18410134

申请日：2024-01-11

Applicant: Samsung Display Co., LTD.

Inventor： Joon Yong PARK ,  Hyun Eok SHIN ,  Su Kyoung YANG ,  Dong Min LEE

IPC: H10K59/122 ,  H10K59/12 ,  H10K59/126 ,  H10K59/38 ,  H10K59/40 ,  H10K71/20 ,  H10K71/60 ,  H10K102/00

Abstract: A display device includes an emission area including a pixel electrode, an inorganic layer exposing the pixel electrode to outside the inorganic layer, a light emitting layer and a common electrode, and a bank layer on the inorganic layer and in which an opening is defined corresponding to the emission area. The bank layer includes a first bank layer including zinc, a second bank layer on the first bank layer, a third bank layer on the second bank layer, each of the first bank layer, the second bank layer and the third bank layer including a side surface which defines a portion of the opening in the bank layer; the side surface of the first bank layer recessed from the side surface of the second bank layer in a direction away from the first emission area; and the side surface of the second bank layer recessed from the side surface of the first bank layer in a direction away from the emission area.

公开(公告)号：US20190088752A1

公开(公告)日：2019-03-21

申请号：US16192802

申请日：2018-11-16

Applicant: Samsung Display Co., Ltd.

Inventor： Chan Woo YANG ,  Hyune Ok SHIN ,  Chang Oh JEONG ,  Su Kyoung YANG ,  Dong Min LEE

IPC: H01L29/417 ,  H01L27/12 ,  H01L29/786 ,  H01L29/24 ,  H01L29/45 ,  C22C29/12

Abstract: A thin film transistor includes a gate electrode, a semiconductor layer, and source and drain electrodes contacting the semiconductor layer. The source and drain electrodes include a metal oxide having a crystal size in a c-axis direction Lc(002) that ranges from 67 Å or more to 144 ∈ or less.

公开(公告)号：US20160293633A1

公开(公告)日：2016-10-06

申请号：US14926416

申请日：2015-10-29

Applicant: Samsung Display Co., Ltd.

Inventor： Chan Woo YANG ,  Hyun Eok SHIN ,  Su Kyoung YANG ,  Dong Min LEE

IPC: H01L27/12 ,  G02F1/1368 ,  G02F1/1362 ,  H01L29/786

CPC classification number: H01L27/124 ,  H01L27/1225 ,  H01L27/1262 ,  H01L27/1288 ,  H01L29/7869 ,  H01L29/78696

Abstract: A thin-film transistor array panel includes a gate line disposed on a first substrate, the gate line including a gate electrode, a semiconductor layer disposed on the first substrate, the semiconductor layer including an oxide semiconductor, a data wire layer disposed on the first substrate, the data wire layer including a data line crossing the gate line, a source electrode connected to the data line, and a drain electrode facing the source electrode, a capping layer disposed on the data wire layer, a tilt layer disposed on the capping layer, and a passivation layer disposed on the tilt layer, in which the tilt layer includes a silsesquioxane-based copolymer.

Abstract translation: 薄膜晶体管阵列面板包括设置在第一基板上的栅极线，栅极线包括栅电极，设置在第一基板上的半导体层，包括氧化物半导体的半导体层，设置在第一基板上的数据线层 基板，包括与栅极线交叉的数据线的数据线层，连接到数据线的源电极和面对源电极的漏电极，设置在数据线层上的覆盖层，设置在封盖上的倾斜层 层和设置在倾斜层上的钝化层，其中倾斜层包括倍半硅氧烷基共聚物。